From 5bc6bd4c41591b9b322436519275dfadd5096474 Mon Sep 17 00:00:00 2001 From: Morris Hsu Date: Fri, 9 Aug 2024 14:53:20 +0800 Subject: mb/google/brox/jubilant: update overridetree for dptf settings Update dptf settings for EVT. BUG=None TEST=emerge-brox coreboot chromeos-bootiamge Change-Id: Iadc95c14da6f879e25dac4804907e340dc16e47f Signed-off-by: Morris Hsu Reviewed-on: https://review.coreboot.org/c/coreboot/+/83842 Reviewed-by: Ren Kuo Tested-by: build bot (Jenkins) --- src/mainboard/google/brox/variants/jubilant/overridetree.cb | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) (limited to 'src/mainboard/google/brox/variants') diff --git a/src/mainboard/google/brox/variants/jubilant/overridetree.cb b/src/mainboard/google/brox/variants/jubilant/overridetree.cb index d4deb92eca..4110f437da 100644 --- a/src/mainboard/google/brox/variants/jubilant/overridetree.cb +++ b/src/mainboard/google/brox/variants/jubilant/overridetree.cb @@ -41,8 +41,9 @@ chip soc/intel/alderlake device ref dtt on chip drivers/intel/dptf ## sensor information - register "options.tsr[0].desc" = ""DRAM_SOC"" - register "options.tsr[1].desc" = ""Fan-Inlet"" + register "options.tsr[0].desc" = ""DRAM"" + register "options.tsr[1].desc" = ""Soc"" + register "options.tsr[2].desc" = ""Charger"" ## Active Policy register "policies.active" = "{ @@ -101,7 +102,7 @@ chip soc/intel/alderlake register "controls.power_limits" = "{ .pl1 = { .min_power = 15000, - .max_power = 15000, + .max_power = 18000, .time_window_min = 28 * MSECS_PER_SEC, .time_window_max = 32 * MSECS_PER_SEC, .granularity = 200, -- cgit v1.2.3