From 8cfe1b3302ff2d6e1fcce7508627529b3a80dc6d Mon Sep 17 00:00:00 2001 From: Ren Kuo Date: Thu, 29 Aug 2024 10:14:40 +0800 Subject: mb/google/brox/jubilant: Modify FP IRQ pin to GPP_D13 Modify the FP IRQ pin to GPP_D13 from GPP_F15 from HW change on EVT. The design change to follow the brox's GPE0 routing, and the FP wake source can be routed. BUG=b:363166664 TEST= Build jubilant firmware Change-Id: Ic4a7ca07eab0dab234ab025cf77bbb8093b6b9d1 Signed-off-by: Ren Kuo Reviewed-on: https://review.coreboot.org/c/coreboot/+/84124 Reviewed-by: Subrata Banik Reviewed-by: Kenneth Chan Tested-by: build bot (Jenkins) --- src/mainboard/google/brox/variants/jubilant/overridetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mainboard/google/brox/variants/jubilant/overridetree.cb') diff --git a/src/mainboard/google/brox/variants/jubilant/overridetree.cb b/src/mainboard/google/brox/variants/jubilant/overridetree.cb index d1fbb8bebd..2f6f83b6f8 100644 --- a/src/mainboard/google/brox/variants/jubilant/overridetree.cb +++ b/src/mainboard/google/brox/variants/jubilant/overridetree.cb @@ -399,8 +399,8 @@ chip soc/intel/alderlake register "hid" = "ACPI_DT_NAMESPACE_HID" register "uid" = "1" register "compat_string" = ""google,cros-ec-spi"" - register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)" - register "wake" = "GPE0_DW2_15" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_D13_IRQ)" + register "wake" = "GPE0_DW1_13" register "has_power_resource" = "1" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)" register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)" -- cgit v1.2.3