From e8abb5ab8887969498f9953e76b7e0f4c68d3e47 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 15 Apr 2020 15:01:53 +0200 Subject: nb/intel/haswell: Deprecate WDB params in pei_data The WDB (Write Data Buffer) is a data region in CAR, used as a scratchpad in the read and write training algorithms of memory initialization. Both SNB and IVB use this buffer, but HSW does not. Unlike earlier chipsets, Haswell contains much more in-hardware memory training machinery, known as REUT (Robust Electrical Unified Testing). Among other changes, the REUT hardware has a pattern storage buffer, which renders the need for a pattern storage buffer in CAR obsolete. Deprecate the WDB-related parameters in the pei_data structure for Haswell, as they are leftovers from the previous generation's MRC. Remove them from the mainboards, and explain why they are not required. Because the MRC ABI has to remain the same, the layout of pei_data must not be changed, so rename the WDB parameters instead of deleting them. Tested on Asrock B85M Pro4, still boots with the MRC from Google Wolf. Change-Id: I7acc9353a22f8c6f9fe6407617162f35849a79dd Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/40406 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Arthur Heymans --- src/mainboard/google/beltino/romstage.c | 2 -- 1 file changed, 2 deletions(-) (limited to 'src/mainboard/google/beltino') diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index 373b488fe9..263ee32675 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -62,8 +62,6 @@ void mainboard_romstage_entry(void) .epbar = DEFAULT_EPBAR, .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, .smbusbar = SMBUS_IO_BASE, - .wdbbar = 0x4000000, - .wdbsize = 0x1000, .hpet_address = HPET_ADDR, .rcba = (uintptr_t)DEFAULT_RCBA, .pmbase = DEFAULT_PMBASE, -- cgit v1.2.3