From 90ae08922d7f6fdc8b762cb7bc1e2d8d85807854 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 12 Mar 2021 17:00:52 +0100 Subject: nb/intel/haswell: Consolidate memory-down SPD handling Mainboards do not need to know about `pei_data` to tell northbridge code where to find the SPD data. Adjust `mb_get_spd_map` to take a pointer to a struct instead of an array, and update all the mainboards accordingly. Currently, the only board with memory-down in the tree is google/slippy. Mainboard code now obtains the SPD index in `mb_get_spd_map` and adjusts the channel population accordingly. Then, northbridge code reads the SPD file and uses the index that was read in `mb_get_spd_map`, and copies it to channel 0 slot 0 unconditionally. MRC only uses the first position of the `spd_data` array, and ignores the other positions. In coreboot code, `setup_sdram_meminfo` uses the data of each SPD index, so `copy_spd` has to account for this. Tested on Asrock B85M Pro4, still boots and still resumes from S3. Change-Id: Ibaed5c6de9853db6abd08f53bbfda8800d207c3e Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/51448 Reviewed-by: Nico Huber Reviewed-by: Matt DeVillier Tested-by: build bot (Jenkins) --- src/mainboard/google/beltino/romstage.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/mainboard/google/beltino') diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index dda2edc8d5..b69fb933b3 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -40,10 +40,10 @@ void mainboard_config_rcba(void) RCBA16(D23IR) = DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH); /* SDIO */ } -void mb_get_spd_map(uint8_t spd_map[4]) +void mb_get_spd_map(struct spd_info *spdi) { - spd_map[0] = 0xa0; - spd_map[2] = 0xa4; + spdi->addresses[0] = 0xa0; + spdi->addresses[2] = 0xa4; } const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { -- cgit v1.2.3