From 1be9f5841dabd42a740fe23a77ea128fa8d0835d Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 3 Jul 2020 21:31:17 +0200 Subject: haswell: Introduce ENABLE_DDR_2X_REFRESH Kconfig option This Kconfig symbol allows doubling the memory's refresh rate, assuming that the MRC actually cares about it. It is disabled by default except on the mainboards which explicitly enabled this setting in `pei_data`. Change-Id: I6318dad0350d1c506c67f9d117d0ae8dad871281 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/43122 Tested-by: build bot (Jenkins) Reviewed-by: Tristan Corrick --- src/mainboard/google/beltino/Kconfig | 3 +++ src/mainboard/google/beltino/romstage.c | 2 -- 2 files changed, 3 insertions(+), 2 deletions(-) (limited to 'src/mainboard/google/beltino') diff --git a/src/mainboard/google/beltino/Kconfig b/src/mainboard/google/beltino/Kconfig index 4aff149e0d..0c9311f70c 100644 --- a/src/mainboard/google/beltino/Kconfig +++ b/src/mainboard/google/beltino/Kconfig @@ -57,4 +57,7 @@ config MAINBOARD_SMBIOS_MANUFACTURER string default "GOOGLE" +config ENABLE_DDR_2X_REFRESH + default y + endif # BOARD_GOOGLE_BASEBOARD_BELTINO diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index 54295a4597..8b3ace2eea 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -45,8 +45,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) pei_data->spd_addresses[0] = 0xa0; pei_data->spd_addresses[2] = 0xa4; pei_data->ec_present = 0; - /* Enable 2x refresh mode */ - pei_data->ddr_refresh_2x = 1; pei_data->dq_pins_interleaved = 1; pei_data->usb_xhci_on_resume = 1; -- cgit v1.2.3