From 81ae67a634d3bd72b10f798490ee25c3a3cb807a Mon Sep 17 00:00:00 2001
From: Matt DeVillier <matt.devillier@gmail.com>
Date: Tue, 8 Nov 2016 15:04:30 -0600
Subject: Add Haswell Chromeboxes/Chromebase using variant board scheme

Combine existing board google/panther with new ChromeOS devices
mccloud, monroe, tricky, and zako, using their common reference board
(beltino) as a base.

Chromium sources used:
firmware-mccloud-5827.B 65bfee7 [haswell: No need pre-graphics delay...]
firmware-monroe-4921.B 1ac749d [Monroe: Disable KB/MS in ITE8772.]
firmware-tricky-5829.B 2db5322 [haswell: No need pre-graphics delay...]
firmware-zako-5219.B eacedef [haswell: No need pre-graphics delay...]

Existing google/panther board will be removed in a subsequent commit.

Variant setup modeled after google/reef

Change-Id: I5d7e0c2551e8b0707841032460c35615cefb2886
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17329
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
---
 src/mainboard/google/beltino/dsdt.asl | 56 +++++++++++++++++++++++++++++++++++
 1 file changed, 56 insertions(+)
 create mode 100644 src/mainboard/google/beltino/dsdt.asl

(limited to 'src/mainboard/google/beltino/dsdt.asl')

diff --git a/src/mainboard/google/beltino/dsdt.asl b/src/mainboard/google/beltino/dsdt.asl
new file mode 100644
index 0000000000..6393d688fb
--- /dev/null
+++ b/src/mainboard/google/beltino/dsdt.asl
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		// DSDT revision: ACPI v2.0
+	"COREv4",	// OEM id
+	"COREBOOT",	// OEM table id
+	0x20110725	// OEM revision
+)
+{
+	// Some generic macros
+	#include "acpi/platform.asl"
+
+	// global NVS and variables
+	#include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
+
+	// CPU
+	#include <cpu/intel/haswell/acpi/cpu.asl>
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+			#include <northbridge/intel/haswell/acpi/haswell.asl>
+			#include <southbridge/intel/lynxpoint/acpi/pch.asl>
+
+			#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+		}
+	}
+
+	// Mainboard devices
+	#include "acpi/mainboard.asl"
+
+	// Thermal handler
+	#include "acpi/thermal.asl"
+
+	// Chrome OS specific
+	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
+
+	// Chipset specific sleep states
+	#include <southbridge/intel/lynxpoint/acpi/sleepstates.asl>
+}
-- 
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