From 59962f3015055ccf746d286330a8ce4cc8edeccd Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Wed, 1 Aug 2018 13:53:04 -0500 Subject: mb/google/auron,cyan: Remove interrupt from devicetree LPC TPM chip driver These boards require polling vs interrupts, so remove the IRQ definition to prevent it being added to the SSDT device entry. Test: Boot Linux on various auron and cyan variants, verify no error for 'TPM interrupt not working' present in kernel boot log. Change-Id: Ia1139389f075934d41e823ce5190011c90c7cc88 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/27787 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/google/auron/variants/auron_paine/devicetree.cb | 6 +----- src/mainboard/google/auron/variants/auron_yuna/devicetree.cb | 6 +----- src/mainboard/google/auron/variants/gandof/devicetree.cb | 8 ++------ src/mainboard/google/auron/variants/lulu/devicetree.cb | 6 +----- src/mainboard/google/auron/variants/samus/devicetree.cb | 6 +----- 5 files changed, 6 insertions(+), 26 deletions(-) (limited to 'src/mainboard/google/auron') diff --git a/src/mainboard/google/auron/variants/auron_paine/devicetree.cb b/src/mainboard/google/auron/variants/auron_paine/devicetree.cb index 5872cf293c..b31d82979c 100644 --- a/src/mainboard/google/auron/variants/auron_paine/devicetree.cb +++ b/src/mainboard/google/auron/variants/auron_paine/devicetree.cb @@ -91,11 +91,7 @@ chip soc/intel/broadwell device pci 1e.0 off end # PCI bridge device pci 1f.0 on chip drivers/pc80/tpm - # Rising edge interrupt - register "irq_polarity" = "2" - device pnp 0c31.0 on - irq 0x70 = 10 - end + device pnp 0c31.0 on end end chip ec/google/chromeec device pnp 0c09.0 on end diff --git a/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb b/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb index 34051a727f..3c00ec954f 100644 --- a/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb +++ b/src/mainboard/google/auron/variants/auron_yuna/devicetree.cb @@ -91,11 +91,7 @@ chip soc/intel/broadwell device pci 1e.0 off end # PCI bridge device pci 1f.0 on chip drivers/pc80/tpm - # Rising edge interrupt - register "irq_polarity" = "2" - device pnp 0c31.0 on - irq 0x70 = 10 - end + device pnp 0c31.0 on end end chip ec/google/chromeec device pnp 0c09.0 on end diff --git a/src/mainboard/google/auron/variants/gandof/devicetree.cb b/src/mainboard/google/auron/variants/gandof/devicetree.cb index 06ff8ae3b6..118e646ee0 100644 --- a/src/mainboard/google/auron/variants/gandof/devicetree.cb +++ b/src/mainboard/google/auron/variants/gandof/devicetree.cb @@ -90,12 +90,8 @@ chip soc/intel/broadwell device pci 1d.0 on end # USB2 EHCI device pci 1e.0 off end # PCI bridge device pci 1f.0 on - chip drivers/pc80/tpm - # Rising edge interrupt - register "irq_polarity" = "2" - device pnp 0c31.0 on - irq 0x70 = 10 - end + chip drivers/pc80/tpm + device pnp 0c31.0 on end end chip ec/google/chromeec device pnp 0c09.0 on end diff --git a/src/mainboard/google/auron/variants/lulu/devicetree.cb b/src/mainboard/google/auron/variants/lulu/devicetree.cb index 84fc8c450c..622ea3488d 100644 --- a/src/mainboard/google/auron/variants/lulu/devicetree.cb +++ b/src/mainboard/google/auron/variants/lulu/devicetree.cb @@ -92,11 +92,7 @@ chip soc/intel/broadwell device pci 1e.0 off end # PCI bridge device pci 1f.0 on chip drivers/pc80/tpm - # Rising edge interrupt - register "irq_polarity" = "2" - device pnp 0c31.0 on - irq 0x70 = 10 - end + device pnp 0c31.0 on end end chip ec/google/chromeec device pnp 0c09.0 on end diff --git a/src/mainboard/google/auron/variants/samus/devicetree.cb b/src/mainboard/google/auron/variants/samus/devicetree.cb index d12762d60c..a6c2feae56 100644 --- a/src/mainboard/google/auron/variants/samus/devicetree.cb +++ b/src/mainboard/google/auron/variants/samus/devicetree.cb @@ -95,11 +95,7 @@ chip soc/intel/broadwell device pci 1e.0 off end # PCI bridge device pci 1f.0 on chip drivers/pc80/tpm - # Rising edge interrupt - register "irq_polarity" = "2" - device pnp 0c31.0 on - irq 0x70 = 10 - end + device pnp 0c31.0 on end end chip ec/google/chromeec device pnp 0c09.0 on end -- cgit v1.2.3