From 45e11aa0a573aba1e4d8ae8dcd2cc87a8ca87dab Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Sun, 18 Dec 2016 11:59:58 -0600 Subject: Add/Combine Broadwell Chromebooks using variant board scheme Combine existing boards google/auron_paine and google/samus with new ChromeOS devices auron_yuna, gandof and lulu, using their common reference board (auron) as a base. Chromium sources used: firmware-yuna-6301.59.B 6ed8b9d [CHERRY-PICK: broadwell: Update to...] firmware-gandof-6301.155.B 666f34f [gandof: modify power limiting for...] firmware-lulu-6301.136.B 8811714 [lulu: update RAMID table] Additionally, some minor cleanup/changes were made: - I2C devices set to use level (vs edge) interrupt triggering - HDA verb entries use simplified macro entry format - correct FADT table header version - remove unused ACPI device entries / .asl file(s) - clean up ACPI code (e.g., trackpad on Lulu) - adjust _CID for trackpad on Lulu in order to not load non-functional Windows driver (does not affect Linux) - remove unused header includes (multiple/various) - correct I2C addresses used for SMBIOS device entries - correct misc typos etc The existing auron_paine samus boards are removed. Variant setup modeled after google/slippy Change-Id: I53436878d141715eb18b8ea5043d71e6e8728fe8 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/17917 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- .../google/auron/variants/samus/Makefile.inc | 15 ++ .../google/auron/variants/samus/board_version.c | 33 +++ .../google/auron/variants/samus/devicetree.cb | 112 ++++++++++ .../samus/include/variant/acpi/mainboard.asl | 247 +++++++++++++++++++++ .../variants/samus/include/variant/board_version.h | 26 +++ .../auron/variants/samus/include/variant/gpio.h | 120 ++++++++++ .../variants/samus/include/variant/hda_verb.h | 20 ++ .../auron/variants/samus/include/variant/onboard.h | 32 +++ .../auron/variants/samus/include/variant/spd.h | 40 ++++ .../auron/variants/samus/include/variant/thermal.h | 35 +++ .../google/auron/variants/samus/pei_data.c | 77 +++++++ .../google/auron/variants/samus/spd/Makefile.inc | 50 +++++ .../auron/variants/samus/spd/elpida_16.spd.hex | 18 ++ .../auron/variants/samus/spd/elpida_4.spd.hex | 16 ++ .../auron/variants/samus/spd/elpida_8.spd.hex | 16 ++ .../google/auron/variants/samus/spd/empty.spd.hex | 16 ++ .../auron/variants/samus/spd/hynix_16.spd.hex | 18 ++ .../auron/variants/samus/spd/hynix_4.spd.hex | 18 ++ .../auron/variants/samus/spd/hynix_8.spd.hex | 18 ++ .../auron/variants/samus/spd/samsung_4.spd.hex | 16 ++ .../auron/variants/samus/spd/samsung_8.spd.hex | 16 ++ .../google/auron/variants/samus/spd/spd.c | 127 +++++++++++ .../google/auron/variants/samus/variant.c | 51 +++++ 23 files changed, 1137 insertions(+) create mode 100644 src/mainboard/google/auron/variants/samus/Makefile.inc create mode 100644 src/mainboard/google/auron/variants/samus/board_version.c create mode 100644 src/mainboard/google/auron/variants/samus/devicetree.cb create mode 100644 src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl create mode 100644 src/mainboard/google/auron/variants/samus/include/variant/board_version.h create mode 100644 src/mainboard/google/auron/variants/samus/include/variant/gpio.h create mode 100644 src/mainboard/google/auron/variants/samus/include/variant/hda_verb.h create mode 100644 src/mainboard/google/auron/variants/samus/include/variant/onboard.h create mode 100644 src/mainboard/google/auron/variants/samus/include/variant/spd.h create mode 100644 src/mainboard/google/auron/variants/samus/include/variant/thermal.h create mode 100644 src/mainboard/google/auron/variants/samus/pei_data.c create mode 100644 src/mainboard/google/auron/variants/samus/spd/Makefile.inc create mode 100644 src/mainboard/google/auron/variants/samus/spd/elpida_16.spd.hex create mode 100644 src/mainboard/google/auron/variants/samus/spd/elpida_4.spd.hex create mode 100644 src/mainboard/google/auron/variants/samus/spd/elpida_8.spd.hex create mode 100644 src/mainboard/google/auron/variants/samus/spd/empty.spd.hex create mode 100644 src/mainboard/google/auron/variants/samus/spd/hynix_16.spd.hex create mode 100644 src/mainboard/google/auron/variants/samus/spd/hynix_4.spd.hex create mode 100644 src/mainboard/google/auron/variants/samus/spd/hynix_8.spd.hex create mode 100644 src/mainboard/google/auron/variants/samus/spd/samsung_4.spd.hex create mode 100644 src/mainboard/google/auron/variants/samus/spd/samsung_8.spd.hex create mode 100644 src/mainboard/google/auron/variants/samus/spd/spd.c create mode 100644 src/mainboard/google/auron/variants/samus/variant.c (limited to 'src/mainboard/google/auron/variants/samus') diff --git a/src/mainboard/google/auron/variants/samus/Makefile.inc b/src/mainboard/google/auron/variants/samus/Makefile.inc new file mode 100644 index 0000000000..6e776fff65 --- /dev/null +++ b/src/mainboard/google/auron/variants/samus/Makefile.inc @@ -0,0 +1,15 @@ +## +## This file is part of the coreboot project. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += board_version.c +ramstage-y += board_version.c diff --git a/src/mainboard/google/auron/variants/samus/board_version.c b/src/mainboard/google/auron/variants/samus/board_version.c new file mode 100644 index 0000000000..c45b84e9e2 --- /dev/null +++ b/src/mainboard/google/auron/variants/samus/board_version.c @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include + +const char *samus_board_version(void) +{ + switch (google_chromeec_get_board_version()) { + case SAMUS_EC_BOARD_VERSION_EVT1: + return "EVT1"; + case SAMUS_EC_BOARD_VERSION_EVT2: + return "EVT2"; + case SAMUS_EC_BOARD_VERSION_EVT3: + return "EVT3"; + case SAMUS_EC_BOARD_VERSION_EVT4: + return "EVT4"; + default: + return "Unknown"; + } +} diff --git a/src/mainboard/google/auron/variants/samus/devicetree.cb b/src/mainboard/google/auron/variants/samus/devicetree.cb new file mode 100644 index 0000000000..d12762d60c --- /dev/null +++ b/src/mainboard/google/auron/variants/samus/devicetree.cb @@ -0,0 +1,112 @@ +chip soc/intel/broadwell + + # Enable eDP Hotplug with 6ms pulse + register "gpu_dp_d_hotplug" = "0x06" + + # Enable DDI1 Hotplug with 6ms pulse + register "gpu_dp_b_hotplug" = "0x06" + + # Enable DDI2 Hotplug with 6ms pulse + register "gpu_dp_c_hotplug" = "0x06" + + # Set backlight PWM values for eDP + register "gpu_cpu_backlight" = "0x00000200" + register "gpu_pch_backlight" = "0x04000200" + + # Enable Panel and configure power delays + register "gpu_panel_port_select" = "1" # eDP + register "gpu_panel_power_cycle_delay" = "6" # 500ms + register "gpu_panel_power_up_delay" = "2000" # 200ms + register "gpu_panel_power_down_delay" = "500" # 50ms + register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms + register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms + + register "pirqa_routing" = "0x8b" + register "pirqb_routing" = "0x8a" + register "pirqc_routing" = "0x8b" + register "pirqd_routing" = "0x8b" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x80" + + # EC range is 0x800-0x9ff + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x00fc0901" + + # EC_SMI is GPIO34 + register "alt_gp_smi_en" = "0x0004" + register "gpe0_en_1" = "0x00000000" + # EC_SCI is GPIO36 + register "gpe0_en_2" = "0x00000010" + register "gpe0_en_3" = "0x00000000" + register "gpe0_en_4" = "0x00000000" + + register "sata_port_map" = "0x1" + register "sata_port0_gen3_tx" = "0x72" + register "sio_acpi_mode" = "1" + + # Set I2C0 to 1.8V + register "sio_i2c0_voltage" = "1" + + # Force enable ASPM for PCIe Port 3 + register "pcie_port_force_aspm" = "0x04" + register "pcie_port_coalesce" = "1" + + # Disable PCIe CLKOUT 1-5 and CLKOUT_XDP + register "icc_clock_disable" = "0x013b0000" + + # Disable S0ix for now + register "s0ix_enable" = "0" + + register "vr_slow_ramp_rate_set" = "3" + register "vr_slow_ramp_rate_enable" = "1" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # host bridge + device pci 02.0 on end # vga controller + device pci 03.0 on end # mini-hd audio + device pci 13.0 on end # Smart Sound Audio DSP + device pci 14.0 on end # USB3 XHCI + device pci 15.0 on end # Serial I/O DMA + device pci 15.1 on end # I2C0 + device pci 15.2 on end # I2C1 + device pci 15.3 on end # GSPI0 + device pci 15.4 off end # GSPI1 + device pci 15.5 off end # UART0 + device pci 15.6 off end # UART1 + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 17.0 off end # SDIO + device pci 19.0 off end # GbE + device pci 1b.0 off end # High Definition Audio + device pci 1c.0 off end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1d.0 off end # USB2 EHCI + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on + chip drivers/pc80/tpm + # Rising edge interrupt + register "irq_polarity" = "2" + device pnp 0c31.0 on + irq 0x70 = 10 + end + end + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end # LPC bridge + device pci 1f.2 on end # SATA Controller + device pci 1f.3 off end # SMBus + device pci 1f.6 on end # Thermal + end +end diff --git a/src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl b/src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000000..40a4df051c --- /dev/null +++ b/src/mainboard/google/auron/variants/samus/include/variant/acpi/mainboard.asl @@ -0,0 +1,247 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#undef ENABLE_TOUCH_WAKE + +Scope (\_SB.PCI0.I2C0) +{ + Device (ATPA) + { + Name (_HID, "ATML0000") + Name (_DDN, "Atmel Touchpad") + Name (_UID, 2) + Name (_S0W, 4) + Name (ISTP, 1) /* Touchpad */ + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + BOARD_TRACKPAD_I2C_ADDR, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\\_SB.PCI0.I2C0", // ResourceSource + ) + + // GPIO13 is PIRQL + Interrupt (ResourceConsumer, Level, ActiveLow) { 27 } + }) + + Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 3 }) + + Method (_DSW, 3, NotSerialized) + { + Store (BOARD_TRACKPAD_WAKE_GPIO, Local0) + If (LEqual (Arg0, 1)) { + // Enable GPIO as wake source + \_SB.PCI0.LPCB.GPIO.GWAK (Local0) + } + } + + Method (_STA) + { + If (LEqual (\S1EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + } + + Device (CODC) + { + /* + * TODO(kane): Need official HID. + * + */ + Name (_HID, "RT5677CE") + Name (_DDN, "RT5667 Codec") + Name (_UID, 1) + + Name (MB1, 1) /* MICBIAS1 = 2.970V */ + Name (DACR, 1) /* Use codec internal 1.8V as DACREF source */ + Name (DCLK, 0) /* RT5677_DMIC_CLK1 */ + Name (PCLK, 1) /* RT5677_PDM_CLK_DIV2 (~3MHz) */ + Name (IN1, 1) /* IN1 differential */ + Name (IN2, 0) /* IN2 not differential */ + Name (OUT1, 1) /* LOUT1 differential */ + Name (OUT2, 1) /* LOUT2 differential */ + Name (OUT3, 0) /* LOUT3 differential */ + Name (ASRC, 1) /* Enable I2S1 ASRC */ + Name (JD1, 0) /* JackDetect1 is not used */ + Name (JD2, 2) /* Use GPIO5 as JackDetect2 */ + Name (JD3, 3) /* Use GPIO6 as JackDetect3 */ + + /* Add DT style bindings with _DSD */ + Name (_DSD, Package () { + ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { "realtek,micbias1", 1 }, + Package () { "realtek,internal-dacref-en", 1 }, + Package () { "realtek,in1-differential", 1 }, + Package () { "realtek,in2-differential", 0 }, + Package () { "realtek,lout1-differential", 1 }, + Package () { "realtek,lout2-differential", 1 }, + Package () { "realtek,lout3-differential", 0 }, + Package () { "realtek,pdm_clk_div", 1 }, + Package () { "realtek,dmic2_clk_pin", 0 }, + Package () { "realtek,asrc-en", 1 }, + Package () { "realtek,jd1-gpio", 0 }, + Package () { "realtek,jd2-gpio", 2 }, + Package () { "realtek,jd3-gpio", 3 }, + Package () { "realtek,gpio-config", + Package () { 0, 0, 0, 0, 0, 2 } }, + } + }) + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + BOARD_CODEC_I2C_ADDR, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\\_SB.PCI0.I2C0", // ResourceSource + ) + + /* GPIO46 is PIRQO (use HOTWORD_DET as codec IRQ) */ + Interrupt (ResourceConsumer, Edge, ActiveHigh) { 30 } + + /* + * Codec GPIOs are 1-based in the schematic + * + * [0] = Jack Detect (INPUT) + * [1] = Mic Present (INPUT) + * [2] = Interrupt to the host (OUTPUT) + * [3] = Interrupt to the host (OUTPUT) + * [4] = Headphone amp control (OUTPUT) + */ + + /* Index 0: Jack Detect - PLUG_DET is GPIO5 */ + GpioIo (Exclusive, PullUp, , , IoRestrictionInputOnly, + "\\_SB.PCI0.I2C0.CODC") { 4 } + + /* Index 1: Mic Present - MIC_PRESENT_L is GPIO6 */ + GpioIo (Exclusive, PullUp, , , IoRestrictionInputOnly, + "\\_SB.PCI0.I2C0.CODC") { 5 } + + /* Index 2: Codec IRQ - HOTWORD_DET_L is GPIO1 */ + GpioIo (Exclusive, PullUp, , , IoRestrictionOutputOnly, + "\\_SB.PCI0.I2C0.CODC") { 0 } + + /* Index 3: Codec Wake - DSP_INT is GPIO4 */ + GpioIo (Exclusive, PullUp, , , IoRestrictionOutputOnly, + "\\_SB.PCI0.I2C0.CODC") { 3 } + + /* Index 4: Headphone amp - HP_AMP_SHDN_L is GPIO2 */ + GpioIo (Exclusive, PullDown, , , IoRestrictionOutputOnly, + "\\_SB.PCI0.I2C0.CODC") { 1 } + }) + + Name (_PRW, Package() { BOARD_CODEC_WAKE_GPIO, 3 }) + + Method (_DSW, 3, NotSerialized) + { + Store (BOARD_CODEC_WAKE_GPIO, Local0) + If (LEqual (Arg0, 1)) { + // Enable GPIO as wake source + \_SB.PCI0.LPCB.GPIO.GWAK (Local0) + } + } + + Method (_STA) + { + If (LEqual (\S1EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + } +} + +Scope (\_SB.PCI0.I2C1) +{ + Device (ATSA) + { + Name (_HID, "ATML0001") + Name (_DDN, "Atmel Touchscreen") + Name (_UID, 5) + Name (_S0W, 4) + Name (ISTP, 0) /* TouchScreen */ + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + BOARD_TOUCHSCREEN_I2C_ADDR, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\\_SB.PCI0.I2C1", // ResourceSource + ) + + // GPIO14 is PIRQM + Interrupt (ResourceConsumer, Level, ActiveLow) { 28 } + }) + +#ifdef ENABLE_TOUCH_WAKE + Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 3 }) + + Method (_DSW, 3, NotSerialized) + { + Store (BOARD_CODEC_WAKE_GPIO, Local0) + If (LEqual (Arg0, 1)) { + // Enable GPIO as wake source + \_SB.PCI0.LPCB.GPIO.GWAK (Local0) + } + } +#endif + + Method (_STA) + { + If (LEqual (\S2EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + } +} + +Scope (\_SB.PCI0.SPI0) +{ + Device (CODC) + { + // TODO: Need official HID. + Name (_HID, "RT5677AA") + Name (_UID, 1) + Name (_CRS, ResourceTemplate () + { + SpiSerialBus ( + 0, // DeviceSelection (CS0?) + PolarityLow, // DeviceSelectionPolarity + FourWireMode, // WireMode + 8, // DataBitLength + ControllerInitiated, // SlaveMode + 1000000, // ConnectionSpeed (1MHz) + ClockPolarityLow, // ClockPolarity + ClockPhaseFirst, // ClockPhase + "\\_SB.PCI0.SPI0", // ResourceSource + 0, // ResourceSourceIndex + ResourceConsumer, // ResourceUsage + ) + }) + } +} diff --git a/src/mainboard/google/auron/variants/samus/include/variant/board_version.h b/src/mainboard/google/auron/variants/samus/include/variant/board_version.h new file mode 100644 index 0000000000..f5371a19fa --- /dev/null +++ b/src/mainboard/google/auron/variants/samus/include/variant/board_version.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SAMUS_BOARD_VERSION_H +#define SAMUS_BOARD_VERSION_H + +#define SAMUS_EC_BOARD_VERSION_EVT1 3 +#define SAMUS_EC_BOARD_VERSION_EVT2 4 +#define SAMUS_EC_BOARD_VERSION_EVT3 5 +#define SAMUS_EC_BOARD_VERSION_EVT4 0 + +const char *samus_board_version(void); + +#endif diff --git a/src/mainboard/google/auron/variants/samus/include/variant/gpio.h b/src/mainboard/google/auron/variants/samus/include/variant/gpio.h new file mode 100644 index 0000000000..8362a4dbfb --- /dev/null +++ b/src/mainboard/google/auron/variants/samus/include/variant/gpio.h @@ -0,0 +1,120 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SAMUS_GPIO_H +#define SAMUS_GPIO_H + +#include + +static const struct gpio_config mainboard_gpio_config[] = { + PCH_GPIO_UNUSED, /* 0: UNUSED */ + PCH_GPIO_UNUSED, /* 1: UNUSED */ + PCH_GPIO_UNUSED, /* 2: UNUSED */ + PCH_GPIO_UNUSED, /* 3: UNUSED */ + PCH_GPIO_NATIVE, /* 4: NATIVE: I2C0_SDA_GPIO4 */ + PCH_GPIO_NATIVE, /* 5: NATIVE: I2C0_SCL_GPIO5 */ + PCH_GPIO_NATIVE, /* 6: NATIVE: I2C1_SDA_GPIO6 */ + PCH_GPIO_NATIVE, /* 7: NATIVE: I2C1_SCL_GPIO7 */ + PCH_GPIO_ACPI_SCI, /* 8: PCH_LTE_WAKE_L */ + PCH_GPIO_INPUT_INVERT, /* 9: TRACKPAD_INT_L (WAKE) */ + PCH_GPIO_ACPI_SCI, /* 10: PCH_WLAN_WAKE_L */ + PCH_GPIO_UNUSED, /* 11: UNUSED */ + PCH_GPIO_UNUSED, /* 12: UNUSED */ + PCH_GPIO_PIRQ, /* 13: TRACKPAD_INT_L (PIRQL) */ + PCH_GPIO_PIRQ, /* 14: TOUCH_INT_L (PIRQM) */ + PCH_GPIO_UNUSED, /* 15: UNUSED (STRAP) */ + PCH_GPIO_INPUT, /* 16: PCH_WP */ + PCH_GPIO_UNUSED, /* 17: UNUSED */ + PCH_GPIO_UNUSED, /* 18: UNUSED */ + PCH_GPIO_UNUSED, /* 19: UNUSED */ + PCH_GPIO_NATIVE, /* 20: PCIE_WLAN_CLKREQ_L */ + PCH_GPIO_OUT_HIGH, /* 21: PP3300_SSD_EN */ + PCH_GPIO_UNUSED, /* 22: UNUSED */ + PCH_GPIO_OUT_LOW, /* 23: PP3300_AUTOBAHN_EN */ + PCH_GPIO_UNUSED, /* 24: UNUSED */ + PCH_GPIO_INPUT, /* 25: EC_IN_RW */ + PCH_GPIO_UNUSED, /* 26: UNUSED */ + PCH_GPIO_ACPI_SCI, /* 27: PCH_WAKE_L */ + PCH_GPIO_UNUSED, /* 28: UNUSED */ + PCH_GPIO_UNUSED, /* 29: UNUSED */ + PCH_GPIO_NATIVE, /* 30: NATIVE: PCH_SUSWARN_L */ + PCH_GPIO_NATIVE, /* 31: NATIVE: ACOK_BUF */ + PCH_GPIO_NATIVE, /* 32: NATIVE: LPC_CLKRUN_L */ + PCH_GPIO_NATIVE, /* 33: NATIVE: SSD_DEVSLP */ + PCH_GPIO_ACPI_SMI, /* 34: EC_SMI_L */ + PCH_GPIO_ACPI_SMI, /* 35: PCH_NMI_DBG_L (route in NMI_EN) */ + PCH_GPIO_ACPI_SCI, /* 36: EC_SCI_L */ + PCH_GPIO_UNUSED, /* 37: UNUSED */ + PCH_GPIO_UNUSED, /* 38: UNUSED */ + PCH_GPIO_UNUSED, /* 39: UNUSED */ + PCH_GPIO_NATIVE, /* 40: NATIVE: PCH_USB1_OC_L */ + PCH_GPIO_NATIVE, /* 41: NATIVE: PCH_USB2_OC_L */ + PCH_GPIO_UNUSED, /* 42: WLAN_DISABLE_L */ + PCH_GPIO_OUT_HIGH, /* 43: PP1800_CODEC_EN */ + PCH_GPIO_UNUSED, /* 44: UNUSED */ + PCH_GPIO_ACPI_SCI, /* 45: DSP_INT - Codec Wake */ + PCH_GPIO_PIRQ, /* 46: HOTWORD_DET_L_3V3 (PIRQO) - Codec IRQ */ + PCH_GPIO_OUT_LOW, /* 47: SSD_RESET_L */ + PCH_GPIO_UNUSED, /* 48: UNUSED */ + PCH_GPIO_UNUSED, /* 49: UNUSED */ + PCH_GPIO_UNUSED, /* 50: UNUSED */ + PCH_GPIO_UNUSED, /* 51: UNUSED */ + PCH_GPIO_INPUT, /* 52: SIM_DET */ + PCH_GPIO_UNUSED, /* 53: UNUSED */ + PCH_GPIO_UNUSED, /* 54: UNUSED */ + PCH_GPIO_UNUSED, /* 55: UNUSED */ + PCH_GPIO_UNUSED, /* 56: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 57: CODEC_RESET_L */ + PCH_GPIO_UNUSED, /* 58: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 59: LTE_DISABLE_L */ + PCH_GPIO_UNUSED, /* 60: UNUSED */ + PCH_GPIO_NATIVE, /* 61: NATIVE: PCH_SUS_STAT */ + PCH_GPIO_NATIVE, /* 62: NATIVE: PCH_SUSCLK */ + PCH_GPIO_NATIVE, /* 63: NATIVE: PCH_SLP_S5_L */ + PCH_GPIO_UNUSED, /* 64: UNUSED */ + PCH_GPIO_INPUT, /* 65: RAM_ID3 */ + PCH_GPIO_INPUT, /* 66: RAM_ID3_OLD (STRAP) */ + PCH_GPIO_INPUT, /* 67: RAM_ID0 */ + PCH_GPIO_INPUT, /* 68: RAM_ID1 */ + PCH_GPIO_INPUT, /* 69: RAM_ID2 */ + PCH_GPIO_UNUSED, /* 70: UNUSED */ + PCH_GPIO_NATIVE, /* 71: NATIVE: MODPHY_EN */ + PCH_GPIO_UNUSED, /* 72: UNUSED */ + PCH_GPIO_UNUSED, /* 73: UNUSED */ + PCH_GPIO_UNUSED, /* 74: UNUSED */ + PCH_GPIO_UNUSED, /* 75: UNUSED */ + PCH_GPIO_UNUSED, /* 76: UNUSED */ + PCH_GPIO_UNUSED, /* 77: UNUSED */ + PCH_GPIO_UNUSED, /* 78: UNUSED */ + PCH_GPIO_UNUSED, /* 79: UNUSED */ + PCH_GPIO_UNUSED, /* 80: UNUSED */ + PCH_GPIO_UNUSED, /* 81: UNUSED */ + PCH_GPIO_NATIVE, /* 82: NATIVE: EC_RCIN_L */ + PCH_GPIO_NATIVE, /* 83: GSPI0_CS */ + PCH_GPIO_NATIVE, /* 84: GSPI0_CLK */ + PCH_GPIO_NATIVE, /* 85: GSPI0_MISO */ + PCH_GPIO_NATIVE, /* 86: GSPI0_MOSI (STRAP) */ + PCH_GPIO_UNUSED, /* 87: UNUSED */ + PCH_GPIO_UNUSED, /* 88: UNUSED */ + PCH_GPIO_OUT_HIGH, /* 89: PP3300_SD_EN */ + PCH_GPIO_UNUSED, /* 90: UNUSED */ + PCH_GPIO_UNUSED, /* 91: UNUSED */ + PCH_GPIO_UNUSED, /* 92: UNUSED */ + PCH_GPIO_UNUSED, /* 93: UNUSED */ + PCH_GPIO_UNUSED, /* 94: UNUSED */ + PCH_GPIO_END +}; + +#endif diff --git a/src/mainboard/google/auron/variants/samus/include/variant/hda_verb.h b/src/mainboard/google/auron/variants/samus/include/variant/hda_verb.h new file mode 100644 index 0000000000..5d088790a5 --- /dev/null +++ b/src/mainboard/google/auron/variants/samus/include/variant/hda_verb.h @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include + +const u32 cim_verb_data[0] = {}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/google/auron/variants/samus/include/variant/onboard.h b/src/mainboard/google/auron/variants/samus/include/variant/onboard.h new file mode 100644 index 0000000000..dcbfc6ed43 --- /dev/null +++ b/src/mainboard/google/auron/variants/samus/include/variant/onboard.h @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#define BOARD_TRACKPAD_I2C_ADDR 0x4a +#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4b +#define BOARD_CODEC_I2C_ADDR 0x2c + +#define BOARD_TRACKPAD_WAKE_GPIO 9 /* GPIO9 */ +#define BOARD_WLAN_WAKE_GPIO 10 /* GPIO10 */ +#define BOARD_TOUCHSCREEN_WAKE_GPIO 14 /* GPIO14 */ +#define BOARD_PP3300_AUTOBAHN_GPIO 23 /* GPIO23 */ +#define BOARD_WLAN_DISABLE_GPIO 42 /* GPIO42 */ +#define BOARD_CODEC_WAKE_GPIO 45 /* GPIO45 */ +#define BOARD_SSD_RESET_GPIO 47 /* GPIO47 */ +#define BOARD_LTE_DISABLE_GPIO 59 /* GPIO59 */ + +#endif diff --git a/src/mainboard/google/auron/variants/samus/include/variant/spd.h b/src/mainboard/google/auron/variants/samus/include/variant/spd.h new file mode 100644 index 0000000000..da48521a7e --- /dev/null +++ b/src/mainboard/google/auron/variants/samus/include/variant/spd.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_SPD_H +#define MAINBOARD_SPD_H + +#define SPD_LEN 256 + +#define SPD_DRAM_TYPE 2 +#define SPD_DRAM_DDR3 0x0b +#define SPD_DRAM_LPDDR3 0xf1 +#define SPD_DENSITY_BANKS 4 +#define SPD_ADDRESSING 5 +#define SPD_ORGANIZATION 7 +#define SPD_BUS_DEV_WIDTH 8 +#define SPD_PART_OFF 128 +#define SPD_PART_LEN 18 + +/* Samus board memory configuration GPIOs */ +#define SPD_GPIO_BIT0 69 +#define SPD_GPIO_BIT1 68 +#define SPD_GPIO_BIT2 67 +#define SPD_GPIO_BIT3 65 + +struct pei_data; +void mainboard_fill_spd_data(struct pei_data *pei_data); + +#endif diff --git a/src/mainboard/google/auron/variants/samus/include/variant/thermal.h b/src/mainboard/google/auron/variants/samus/include/variant/thermal.h new file mode 100644 index 0000000000..8019f780ef --- /dev/null +++ b/src/mainboard/google/auron/variants/samus/include/variant/thermal.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef THERMAL_H +#define THERMAL_H + +/* Control TDP Settings */ +#define CTL_TDP_SENSOR_ID 0 /* PECI */ +#define CTL_TDP_POWER_LIMIT 12 /* 12W */ +#define CTL_TDP_THRESHILD_NORMAL 0 /*Normal TDP Threshold*/ +#define CTL_TDP_THRESHOLD_OFF 85 /* Normal at 85C */ +#define CTL_TDP_THRESHOLD_ON 90 /* Limited at 90C */ + +/* Temperature which OS will shutdown at */ +#define CRITICAL_TEMPERATURE 104 + +/* Temperature which OS will throttle CPU */ +#define PASSIVE_TEMPERATURE 95 + +/* Tj_max value for calculating PECI CPU temperature */ +#define MAX_TEMPERATURE 105 + +#endif diff --git a/src/mainboard/google/auron/variants/samus/pei_data.c b/src/mainboard/google/auron/variants/samus/pei_data.c new file mode 100644 index 0000000000..051653f0e6 --- /dev/null +++ b/src/mainboard/google/auron/variants/samus/pei_data.c @@ -0,0 +1,77 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +void mainboard_fill_pei_data(struct pei_data *pei_data) +{ + /* DQ byte map for Samus board */ + const u8 dq_map[2][6][2] = { + { { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 }, + { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } }, + { { 0x0F, 0xF0 }, { 0x00, 0xF0 }, { 0x0F, 0xF0 }, + { 0x0F, 0x00 }, { 0xFF, 0x00 }, { 0xFF, 0x00 } } }; + /* DQS CPU<>DRAM map for Samus board */ + const u8 dqs_map[2][8] = { + { 2, 0, 1, 3, 6, 4, 7, 5 }, + { 2, 1, 0, 3, 6, 5, 4, 7 } }; + + pei_data->ec_present = 1; + + /* One installed DIMM per channel */ + pei_data->dimm_channel0_disabled = 2; + pei_data->dimm_channel1_disabled = 2; + + memcpy(pei_data->dq_map, dq_map, sizeof(dq_map)); + memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map)); + + /* P0: HOST PORT */ + pei_data_usb2_port(pei_data, 0, 0x0080, 1, 0, + USB_PORT_BACK_PANEL); + /* P1: HOST PORT */ + pei_data_usb2_port(pei_data, 1, 0x0080, 1, 1, + USB_PORT_BACK_PANEL); + /* P2: RAIDEN */ + pei_data_usb2_port(pei_data, 2, 0x0080, 1, USB_OC_PIN_SKIP, + USB_PORT_BACK_PANEL); + /* P3: SD CARD */ + pei_data_usb2_port(pei_data, 3, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_INTERNAL); + /* P4: RAIDEN */ + pei_data_usb2_port(pei_data, 4, 0x0080, 1, USB_OC_PIN_SKIP, + USB_PORT_BACK_PANEL); + /* P5: WWAN (Disabled) */ + pei_data_usb2_port(pei_data, 5, 0x0000, 0, USB_OC_PIN_SKIP, + USB_PORT_SKIP); + /* P6: CAMERA */ + pei_data_usb2_port(pei_data, 6, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_INTERNAL); + /* P7: BT */ + pei_data_usb2_port(pei_data, 7, 0x0040, 1, USB_OC_PIN_SKIP, + USB_PORT_INTERNAL); + + /* P1: HOST PORT */ + pei_data_usb3_port(pei_data, 0, 1, 0, 0); + /* P2: HOST PORT */ + pei_data_usb3_port(pei_data, 1, 1, 1, 0); + /* P3: RAIDEN */ + pei_data_usb3_port(pei_data, 2, 1, USB_OC_PIN_SKIP, 0); + /* P4: RAIDEN */ + pei_data_usb3_port(pei_data, 3, 1, USB_OC_PIN_SKIP, 0); +} diff --git a/src/mainboard/google/auron/variants/samus/spd/Makefile.inc b/src/mainboard/google/auron/variants/samus/spd/Makefile.inc new file mode 100644 index 0000000000..6a357c0cf0 --- /dev/null +++ b/src/mainboard/google/auron/variants/samus/spd/Makefile.inc @@ -0,0 +1,50 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +romstage-y += spd.c + +SPD_BIN = $(obj)/spd.bin + +# { GPIO65, GPIO67, GPIO68, GPIO69 } +SPD_SOURCES = empty # 0b0000 +SPD_SOURCES += empty # 0b0001 +SPD_SOURCES += empty # 0b0010 +SPD_SOURCES += empty # 0b0011 +SPD_SOURCES += empty # 0b0100 +SPD_SOURCES += empty # 0b0101 +SPD_SOURCES += samsung_4 # 0b0110 +SPD_SOURCES += empty # 0b0111 +SPD_SOURCES += hynix_4 # 0b1000 +SPD_SOURCES += empty # 0b1001 +SPD_SOURCES += samsung_8 # 0b1010 +SPD_SOURCES += empty # 0b1011 +SPD_SOURCES += hynix_8 # 0b1100 +SPD_SOURCES += hynix_16 # 0b1101 +SPD_SOURCES += empty # 0b1110 +SPD_SOURCES += elpida_16 # 0b1111 + +SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/spd/$(f).spd.hex) + +# Include spd ROM data +$(SPD_BIN): $(SPD_DEPS) + for f in $+; \ + do for c in $$(cat $$f | grep -v ^#); \ + do printf $$(printf '\%o' 0x$$c); \ + done; \ + done > $@ + +cbfs-files-y += spd.bin +spd.bin-file := $(SPD_BIN) +spd.bin-type := spd diff --git a/src/mainboard/google/auron/variants/samus/spd/elpida_16.spd.hex b/src/mainboard/google/auron/variants/samus/spd/elpida_16.spd.hex new file mode 100644 index 0000000000..5594164816 --- /dev/null +++ b/src/mainboard/google/auron/variants/samus/spd/elpida_16.spd.hex @@ -0,0 +1,18 @@ +# Elpida EDFB232A1MA +# banks 8, ranks 2, rows 15, columns 11, density 8192 Mb, x16 +91 20 F1 03 05 1A 05 0A 03 11 01 08 0A 00 50 01 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 80 00 00 00 00 00 A8 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00 +45 44 46 42 32 33 32 41 31 4D 41 2D 47 44 2D 46 +00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/auron/variants/samus/spd/elpida_4.spd.hex b/src/mainboard/google/auron/variants/samus/spd/elpida_4.spd.hex new file mode 100644 index 0000000000..e73ba6201c --- /dev/null +++ b/src/mainboard/google/auron/variants/samus/spd/elpida_4.spd.hex @@ -0,0 +1,16 @@ +92 11 F1 03 04 11 02 0B 03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00 +45 44 46 38 31 33 32 41 33 4D 41 2D 47 44 2D 46 +20 20 32 2E 30 20 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/auron/variants/samus/spd/elpida_8.spd.hex b/src/mainboard/google/auron/variants/samus/spd/elpida_8.spd.hex new file mode 100644 index 0000000000..b790943fdc --- /dev/null +++ b/src/mainboard/google/auron/variants/samus/spd/elpida_8.spd.hex @@ -0,0 +1,16 @@ +92 11 F1 03 04 12 02 0A 03 11 01 08 0A 00 FE 00 +69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00 +45 44 46 41 32 33 32 41 32 4D 41 2D 47 44 2D 46 +20 20 32 2E 30 20 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/auron/variants/samus/spd/empty.spd.hex b/src/mainboard/google/auron/variants/samus/spd/empty.spd.hex new file mode 100644 index 0000000000..9ec39f1ba4 --- /dev/null +++ b/src/mainboard/google/auron/variants/samus/spd/empty.spd.hex @@ -0,0 +1,16 @@ +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/auron/variants/samus/spd/hynix_16.spd.hex b/src/mainboard/google/auron/variants/samus/spd/hynix_16.spd.hex new file mode 100644 index 0000000000..a03d4ed464 --- /dev/null +++ b/src/mainboard/google/auron/variants/samus/spd/hynix_16.spd.hex @@ -0,0 +1,18 @@ +# Hynix H9CCNNNCLTMLAR LPDDR3 +# banks 8, ranks 2, rows 15, columns 11, density 8192 Mb, x16 +91 20 F1 03 05 1A 05 0A 03 11 01 08 0A 00 50 01 +78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00 +00 80 00 00 00 00 00 A8 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 00 00 00 55 00 00 00 00 00 +48 39 43 43 4E 4E 4E 43 4C 54 4D 4C 41 52 00 00 +00 00 00 00 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/auron/variants/samus/spd/hynix_4.spd.hex b/src/mainboard/google/auron/variants/samus/spd/hynix_4.spd.hex new file mode 100644 index 0000000000..93e65a70dd --- /dev/null +++ b/src/mainboard/google/auron/variants/samus/spd/hynix_4.spd.hex @@ -0,0 +1,18 @@ +# Hynix H9CCNNNBLTMLAR-NTM LPDDR3 +# banks 8, ranks 2, rows 14, columns 10, density 4096 Mb, x32 +91 20 F1 03 04 11 05 0B 03 11 01 08 0A 00 50 01 +78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00 +00 80 00 00 00 00 00 A8 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 00 00 00 55 00 00 00 00 00 +48 39 43 43 4E 4E 4E 42 4C 54 4D 4C 41 52 2D 4E +54 4D 00 00 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/auron/variants/samus/spd/hynix_8.spd.hex b/src/mainboard/google/auron/variants/samus/spd/hynix_8.spd.hex new file mode 100644 index 0000000000..15737e443a --- /dev/null +++ b/src/mainboard/google/auron/variants/samus/spd/hynix_8.spd.hex @@ -0,0 +1,18 @@ +# Hynix H9CCNNNBLTMLAR-NTM LPDDR3 +# banks 8, ranks 2, rows 14, columns 11, density 4096 Mb, x16 +91 20 F1 03 04 12 05 0A 03 11 01 08 0A 00 50 01 +78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00 +00 80 00 00 00 00 00 A8 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 AD 00 00 00 55 00 00 00 00 00 +48 39 43 43 4E 4E 4E 42 4C 54 4D 4C 41 52 2D 4E +54 4D 00 00 80 AD 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/auron/variants/samus/spd/samsung_4.spd.hex b/src/mainboard/google/auron/variants/samus/spd/samsung_4.spd.hex new file mode 100644 index 0000000000..4b82a3a6c7 --- /dev/null +++ b/src/mainboard/google/auron/variants/samus/spd/samsung_4.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 04 11 05 0B 03 11 01 08 0A 00 50 01 +78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00 +00 80 00 00 00 00 00 A8 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 11 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 01 00 00 55 00 00 00 00 00 +4B 34 45 38 45 33 30 34 45 44 2D 45 47 43 45 20 +20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/auron/variants/samus/spd/samsung_8.spd.hex b/src/mainboard/google/auron/variants/samus/spd/samsung_8.spd.hex new file mode 100644 index 0000000000..c0a8fca4ea --- /dev/null +++ b/src/mainboard/google/auron/variants/samus/spd/samsung_8.spd.hex @@ -0,0 +1,16 @@ +91 20 F1 03 04 12 05 0A 03 11 01 08 0A 00 50 01 +78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00 +00 80 00 00 00 00 00 A8 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 0F 11 02 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 80 CE 01 00 00 55 00 00 00 00 00 +4B 34 45 36 45 33 30 34 45 44 2D 45 47 43 45 20 +20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/auron/variants/samus/spd/spd.c b/src/mainboard/google/auron/variants/samus/spd/spd.c new file mode 100644 index 0000000000..dd632f30d7 --- /dev/null +++ b/src/mainboard/google/auron/variants/samus/spd/spd.c @@ -0,0 +1,127 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static void mainboard_print_spd_info(uint8_t spd[]) +{ + const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; + const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 0 }; + const int spd_rows[8] = { 12, 13, 14, 15, 16, -1, -1, -1 }; + const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 }; + const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; + const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; + const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; + char spd_name[SPD_PART_LEN+1] = { 0 }; + + int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7]; + int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; + int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7]; + int cols = spd_cols[spd[SPD_ADDRESSING] & 7]; + int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7]; + int devw = spd_devw[spd[SPD_ORGANIZATION] & 7]; + int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7]; + + /* Module type */ + printk(BIOS_INFO, "SPD: module type is "); + switch (spd[SPD_DRAM_TYPE]) { + case SPD_DRAM_DDR3: + printk(BIOS_INFO, "DDR3\n"); + break; + case SPD_DRAM_LPDDR3: + printk(BIOS_INFO, "LPDDR3\n"); + break; + default: + printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]); + break; + } + + /* Module Part Number */ + memcpy(spd_name, &spd[SPD_PART_OFF], SPD_PART_LEN); + spd_name[SPD_PART_LEN] = 0; + printk(BIOS_INFO, "SPD: module part is %s\n", spd_name); + + printk(BIOS_INFO, "SPD: banks %d, ranks %d, rows %d, columns %d, " + "density %d Mb\n", banks, ranks, rows, cols, capmb); + printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n", + devw, busw); + + if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) { + /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */ + printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n", + capmb / 8 * busw / devw * ranks); + } +} + +/* Copy SPD data for on-board memory */ +void mainboard_fill_spd_data(struct pei_data *pei_data) +{ + int spd_bits[4] = { + SPD_GPIO_BIT0, + SPD_GPIO_BIT1, + SPD_GPIO_BIT2, + SPD_GPIO_BIT3 + }; + int spd_gpio[4]; + int spd_index; + size_t spd_file_len; + char *spd_file; + + spd_gpio[0] = get_gpio(spd_bits[0]); + spd_gpio[1] = get_gpio(spd_bits[1]); + spd_gpio[2] = get_gpio(spd_bits[2]); + spd_gpio[3] = get_gpio(spd_bits[3]); + + spd_index = (spd_gpio[3] << 3) | (spd_gpio[2] << 2) | + (spd_gpio[1] << 1) | spd_gpio[0]; + + printk(BIOS_DEBUG, "SPD: index %d (GPIO%d=%d GPIO%d=%d " + "GPIO%d=%d GPIO%d=%d)\n", spd_index, + spd_bits[3], spd_gpio[3], spd_bits[2], spd_gpio[2], + spd_bits[1], spd_gpio[1], spd_bits[0], spd_gpio[0]); + + spd_file = cbfs_boot_map_with_leak("spd.bin", 0xab, &spd_file_len); + if (!spd_file) + die("SPD data not found."); + + if (spd_file_len < ((spd_index + 1) * SPD_LEN)) { + printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); + spd_index = 0; + } + + if (spd_file_len < SPD_LEN) + die("Missing SPD data."); + + /* Assume same memory in both channels */ + spd_index *= SPD_LEN; + memcpy(pei_data->spd_data[0][0], spd_file + spd_index, SPD_LEN); + memcpy(pei_data->spd_data[1][0], spd_file + spd_index, SPD_LEN); + + /* Make sure a valid SPD was found */ + if (pei_data->spd_data[0][0][0] == 0) + die("Invalid SPD data."); + + mainboard_print_spd_info(pei_data->spd_data[0][0]); +} diff --git a/src/mainboard/google/auron/variants/samus/variant.c b/src/mainboard/google/auron/variants/samus/variant.c new file mode 100644 index 0000000000..e711b60f26 --- /dev/null +++ b/src/mainboard/google/auron/variants/samus/variant.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +const char *smbios_mainboard_version(void) +{ + return samus_board_version(); +} + +int variant_smbios_data(device_t dev, int *handle, + unsigned long *current) +{ + /* N/A for SAMUS */ + return 0; +} + +void variant_romstage_entry(struct romstage_params *rp) +{ + if (rp->power_state->prev_sleep_state != ACPI_S3) + google_chromeec_kbbacklight(100); + + printk(BIOS_INFO, "MLB: board version %s\n", samus_board_version()); + + /* Bring SSD out of reset */ + set_gpio(BOARD_SSD_RESET_GPIO, GPIO_OUT_HIGH); + + /* + * Enable PP3300_AUTOBAHN_EN after initial GPIO setup + * to prevent possible brownout. + */ + set_gpio(BOARD_PP3300_AUTOBAHN_GPIO, GPIO_OUT_HIGH); +} \ No newline at end of file -- cgit v1.2.3