From 739a6ad1ac098231c34587c69237906e721b7e91 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 29 Oct 2020 11:02:21 +0100 Subject: mb/google/auron: Use Haswell CPU code The VR config and S0ix options are now specified for the CPU chip. Change-Id: I75e405d41b4a0605e786fe761c92535e62d0cfce Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46945 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- .../google/auron/variants/samus/overridetree.cb | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) (limited to 'src/mainboard/google/auron/variants/samus/overridetree.cb') diff --git a/src/mainboard/google/auron/variants/samus/overridetree.cb b/src/mainboard/google/auron/variants/samus/overridetree.cb index 34a785b711..0a92efe70b 100644 --- a/src/mainboard/google/auron/variants/samus/overridetree.cb +++ b/src/mainboard/google/auron/variants/samus/overridetree.cb @@ -12,11 +12,20 @@ chip soc/intel/broadwell .backlight_pwm_hz = 200, }" - register "vr_slow_ramp_rate_set" = "3" - register "vr_slow_ramp_rate_enable" = "1" - - # Disable S0ix for now - register "s0ix_enable" = "0" + device cpu_cluster 0 on + chip cpu/intel/haswell + # Disable S0ix for now + register "s0ix_enable" = "0" + + register "vr_config" = "{ + .slow_ramp_rate_set = 3, + .slow_ramp_rate_enable = true, + }" + + device lapic 0 on end + device lapic 0xacac off end + end + end device domain 0 on chip soc/intel/broadwell/pch -- cgit v1.2.3