From 99af210456d346187692e0b7b982b01c28006ab0 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 23 Oct 2020 20:39:17 +0200 Subject: mb/google/auron: Prepare devicetree for PCH split Tested with BUILD_TIMELESS=1, all variants remain identical. Change-Id: I2b088b36c8e9ff9cbd47d625b14fc45ebd96532a Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46702 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/mainboard/google/auron/variants/lulu/overridetree.cb | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) (limited to 'src/mainboard/google/auron/variants/lulu') diff --git a/src/mainboard/google/auron/variants/lulu/overridetree.cb b/src/mainboard/google/auron/variants/lulu/overridetree.cb index 60aef30a58..dc70085dd0 100644 --- a/src/mainboard/google/auron/variants/lulu/overridetree.cb +++ b/src/mainboard/google/auron/variants/lulu/overridetree.cb @@ -7,9 +7,11 @@ chip soc/intel/broadwell register "gpu_panel_power_backlight_on_delay" = "70" # 7ms register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms - # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x5" - register "sata_port1_gen3_dtle" = "0x5" - - device domain 0 on end + device domain 0 on +# chip soc/intel/broadwell/pch + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" +# end + end end -- cgit v1.2.3