From d79b87a1d6fcd6228edbd894e7e7ebc9b85d2813 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 25 Oct 2020 16:44:22 +0100 Subject: mb/google/auron: Add SATA PCI device to overridetree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit `chip` entries are only hooked up via device nodes to the tree. A `chip` without a `device` below it does nothing. To allow variants to override SATA tuning parameters, ensure a device exists under the PCH chip scope. Without this change, some variants would not properly override the SATA tuning parameters after extracting the PCH parts into a different chip. TEST=Sanity-check static.c and verify overridetrees override properly. Change-Id: I013dbe1403567b93c8ee0e66f76481f2a3f42796 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46769 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/mainboard/google/auron/variants/gandof/overridetree.cb | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/mainboard/google/auron/variants/gandof') diff --git a/src/mainboard/google/auron/variants/gandof/overridetree.cb b/src/mainboard/google/auron/variants/gandof/overridetree.cb index eae7999ea2..924e7d3c90 100644 --- a/src/mainboard/google/auron/variants/gandof/overridetree.cb +++ b/src/mainboard/google/auron/variants/gandof/overridetree.cb @@ -12,6 +12,8 @@ chip soc/intel/broadwell # DTLE DATA / EDGE values register "sata_port0_gen3_dtle" = "0x5" register "sata_port1_gen3_dtle" = "0x5" + + device pci 1f.2 on end # SATA Controller # end end end -- cgit v1.2.3