From 99af210456d346187692e0b7b982b01c28006ab0 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 23 Oct 2020 20:39:17 +0200 Subject: mb/google/auron: Prepare devicetree for PCH split Tested with BUILD_TIMELESS=1, all variants remain identical. Change-Id: I2b088b36c8e9ff9cbd47d625b14fc45ebd96532a Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/46702 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- .../google/auron/variants/buddy/overridetree.cb | 42 +++++++++++----------- 1 file changed, 22 insertions(+), 20 deletions(-) (limited to 'src/mainboard/google/auron/variants/buddy') diff --git a/src/mainboard/google/auron/variants/buddy/overridetree.cb b/src/mainboard/google/auron/variants/buddy/overridetree.cb index f14896425a..45229bad6d 100644 --- a/src/mainboard/google/auron/variants/buddy/overridetree.cb +++ b/src/mainboard/google/auron/variants/buddy/overridetree.cb @@ -7,32 +7,34 @@ chip soc/intel/broadwell register "gpu_panel_power_backlight_on_delay" = "70" # 7ms register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms - register "sata_devslp_disable" = "0x1" + register "s0ix_enable" = "0" - register "sio_i2c0_voltage" = "1" # 1.8V - register "sio_i2c1_voltage" = "0" # 3.3V + device domain 0 on +# chip soc/intel/broadwell/pch + register "sata_devslp_disable" = "0x1" - # DTLE DATA / EDGE values - register "sata_port0_gen3_dtle" = "0x5" - register "sata_port1_gen3_dtle" = "0x5" + register "sio_i2c0_voltage" = "1" # 1.8V + register "sio_i2c1_voltage" = "0" # 3.3V - # Force enable ASPM for PCIe Port 5 - register "pcie_port_force_aspm" = "0x10" + # DTLE DATA / EDGE values + register "sata_port0_gen3_dtle" = "0x5" + register "sata_port1_gen3_dtle" = "0x5" - # Enable port coalescing - register "pcie_port_coalesce" = "1" + # Force enable ASPM for PCIe Port 5 + register "pcie_port_force_aspm" = "0x10" - # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP - register "icc_clock_disable" = "0x01220000" + # Enable port coalescing + register "pcie_port_coalesce" = "1" - register "s0ix_enable" = "0" + # Disable PCIe CLKOUT 1,5 and CLKOUT_XDP + register "icc_clock_disable" = "0x01220000" - device domain 0 on - device pci 13.0 on end # Smart Sound Audio DSP - device pci 1b.0 off end # High Definition Audio - device pci 1c.0 off end # PCIe Port #1 - device pci 1c.2 on end # PCIe Port #3 - LAN (becomes RP1) - device pci 1c.3 on end # PCIe Port #4 - WLAN (becomes RP2) - device pci 1f.3 on end # SMBus + device pci 13.0 on end # Smart Sound Audio DSP + device pci 1b.0 off end # High Definition Audio + device pci 1c.0 off end # PCIe Port #1 + device pci 1c.2 on end # PCIe Port #3 - LAN (becomes RP1) + device pci 1c.3 on end # PCIe Port #4 - WLAN (becomes RP2) + device pci 1f.3 on end # SMBus +# end end end -- cgit v1.2.3