From d862121fbe6285be2f91a0c09058a22a775c0d19 Mon Sep 17 00:00:00 2001
From: Marc Jones <marc.jones@se-eng.com>
Date: Tue, 9 Jun 2015 21:18:38 -0600
Subject: google/auron: Add mainboard

Add the Google Auron Broadwell Reference Mainboard. It is based
on the Google Peppy mainboard. It was merged from the following
chromium.org commit:  d20a1d1a22d64546a5d8761b18ab29732ec0b848

Change-Id: I716a79e198e91c428bd965fcd03665c2c7067602
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/10500
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
---
 src/mainboard/google/auron/smihandler.c | 56 ++++++++++++++-------------------
 1 file changed, 23 insertions(+), 33 deletions(-)

(limited to 'src/mainboard/google/auron/smihandler.c')

diff --git a/src/mainboard/google/auron/smihandler.c b/src/mainboard/google/auron/smihandler.c
index 5d7df375ae..2f46260f0b 100644
--- a/src/mainboard/google/auron/smihandler.c
+++ b/src/mainboard/google/auron/smihandler.c
@@ -2,7 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2008-2009 coresystems GmbH
- * Copyright 2012 Google Inc.
+ * Copyright 2014 Google Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -21,15 +21,15 @@
 #include <arch/io.h>
 #include <console/console.h>
 #include <cpu/x86/smm.h>
-#include <southbridge/intel/lynxpoint/nvs.h>
-#include <southbridge/intel/lynxpoint/pch.h>
-#include <southbridge/intel/lynxpoint/me.h>
-#include <northbridge/intel/haswell/haswell.h>
-#include <cpu/intel/haswell/haswell.h>
+#include <soc/pm.h>
+#include <soc/smm.h>
 #include <elog.h>
-
-/* Include EC functions */
 #include <ec/google/chromeec/ec.h>
+#include <soc/gpio.h>
+#include <soc/iomap.h>
+#include <soc/nvs.h>
+#include <soc/pm.h>
+#include <soc/smm.h>
 #include "ec.h"
 
 /* Codec enable: GPIO45 */
@@ -37,6 +37,7 @@
 /* WLAN / BT enable: GPIO46 */
 #define GPIO_WLAN_DISABLE_L  46
 
+
 static u8 mainboard_smi_ec(void)
 {
 	u8 cmd = google_chromeec_get_event();
@@ -53,9 +54,9 @@ static u8 mainboard_smi_ec(void)
 		printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
 
 		/* Go to S5 */
-		pm1_cnt = inl(get_pmbase() + PM1_CNT);
+		pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
 		pm1_cnt |= (0xf << 10);
-		outl(pm1_cnt, get_pmbase() + PM1_CNT);
+		outl(pm1_cnt, ACPI_BASE_ADDRESS + PM1_CNT);
 		break;
 	}
 
@@ -67,7 +68,8 @@ void mainboard_smi_gpi(u32 gpi_sts)
 {
 	if (gpi_sts & (1 << (EC_SMI_GPI - 32))) {
 		/* Process all pending events */
-		while (mainboard_smi_ec() != 0);
+		while (mainboard_smi_ec() != 0)
+			;
 	}
 }
 
@@ -76,12 +78,12 @@ void mainboard_smi_sleep(u8 slp_typ)
 	/* Disable USB charging if required */
 	switch (slp_typ) {
 	case 3:
-		if (smm_get_gnvs()->s3u0 == 0)
+		if (smm_get_gnvs()->s3u0 == 0) {
 			google_chromeec_set_usb_charge_mode(
 				0, USB_CHARGE_MODE_DISABLED);
-		if (smm_get_gnvs()->s3u1 == 0)
 			google_chromeec_set_usb_charge_mode(
 				1, USB_CHARGE_MODE_DISABLED);
+		}
 
 		set_gpio(GPIO_PP3300_CODEC_EN, 0);
 		set_gpio(GPIO_WLAN_DISABLE_L, 0);
@@ -90,12 +92,12 @@ void mainboard_smi_sleep(u8 slp_typ)
 		google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
 		break;
 	case 5:
-		if (smm_get_gnvs()->s5u0 == 0)
+		if (smm_get_gnvs()->s5u0 == 0) {
 			google_chromeec_set_usb_charge_mode(
 				0, USB_CHARGE_MODE_DISABLED);
-		if (smm_get_gnvs()->s5u1 == 0)
 			google_chromeec_set_usb_charge_mode(
 				1, USB_CHARGE_MODE_DISABLED);
+		}
 
 		set_gpio(GPIO_PP3300_CODEC_EN, 0);
 		set_gpio(GPIO_WLAN_DISABLE_L, 0);
@@ -110,37 +112,25 @@ void mainboard_smi_sleep(u8 slp_typ)
 	google_chromeec_set_sci_mask(0);
 
 	/* Clear pending events that may trigger immediate wake */
-	while (google_chromeec_get_event() != 0);
+	while (google_chromeec_get_event() != 0)
+		;
 }
 
-
-static int mainboard_finalized = 0;
-
 int mainboard_smi_apmc(u8 apmc)
 {
 	switch (apmc) {
-	case APM_CNT_FINALIZE:
-		if (mainboard_finalized) {
-			printk(BIOS_DEBUG, "SMI#: Already finalized\n");
-			return 0;
-		}
-
-		intel_pch_finalize_smm();
-		intel_northbridge_haswell_finalize_smm();
-		intel_cpu_haswell_finalize_smm();
-
-		mainboard_finalized = 1;
-		break;
 	case APM_CNT_ACPI_ENABLE:
 		google_chromeec_set_smi_mask(0);
 		/* Clear all pending events */
-		while (google_chromeec_get_event() != 0);
+		while (google_chromeec_get_event() != 0)
+			;
 		google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
 		break;
 	case APM_CNT_ACPI_DISABLE:
 		google_chromeec_set_sci_mask(0);
 		/* Clear all pending events */
-		while (google_chromeec_get_event() != 0);
+		while (google_chromeec_get_event() != 0)
+			;
 		google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);
 		break;
 	}
-- 
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