From 4c4bd3cd973f3ec20c3a343a183af4a19b97a748 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 7 Nov 2022 13:30:29 +0100 Subject: soc/intel/broadwell: Hook up PCI domain and CPU cluster ops to devicetree Change-Id: I77a333827552741453d8b575f2a8009b3e1bf8f1 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/69301 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held Reviewed-by: Angel Pons --- src/mainboard/google/auron/devicetree.cb | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/mainboard/google/auron/devicetree.cb') diff --git a/src/mainboard/google/auron/devicetree.cb b/src/mainboard/google/auron/devicetree.cb index 3e2f289145..440efdfd69 100644 --- a/src/mainboard/google/auron/devicetree.cb +++ b/src/mainboard/google/auron/devicetree.cb @@ -15,6 +15,7 @@ chip soc/intel/broadwell register "ec_present" = "true" device cpu_cluster 0 on + ops broadwell_cpu_bus_ops chip cpu/intel/haswell register "s0ix_enable" = "1" @@ -24,6 +25,7 @@ chip soc/intel/broadwell end device domain 0 on + ops broadwell_pci_domain_ops device pci 00.0 on end # host bridge device pci 02.0 on end # vga controller device pci 03.0 on end # mini-hd audio -- cgit v1.2.3