From c70eed1e6202c928803f3e7f79161cd247a62b23 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Tue, 22 May 2018 02:18:00 +0300 Subject: device: Use pcidev_on_root() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Icf34b39d80f6e46d32a39b68f38fb2752c0bcebc Signed-off-by: Kyösti Mälkki Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/26484 Tested-by: build bot (Jenkins) Reviewed-by: Piotr Król Reviewed-by: Arthur Heymans --- src/mainboard/gigabyte/ma785gm/mainboard.c | 6 +++--- src/mainboard/gigabyte/ma785gmt/mainboard.c | 10 +++++----- src/mainboard/gigabyte/ma78gm/mainboard.c | 4 ++-- 3 files changed, 10 insertions(+), 10 deletions(-) (limited to 'src/mainboard/gigabyte') diff --git a/src/mainboard/gigabyte/ma785gm/mainboard.c b/src/mainboard/gigabyte/ma785gm/mainboard.c index 4c9799a510..d11deb082b 100644 --- a/src/mainboard/gigabyte/ma785gm/mainboard.c +++ b/src/mainboard/gigabyte/ma785gm/mainboard.c @@ -40,7 +40,7 @@ void set_pcie_dereset(void) pm_iowrite(0x94, byte); /* set the GPIO65 output enable and the value is 1 */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); word = pci_read_config16(sm_dev, 0x7e); word |= (1 << 0); word &= ~(1 << 4); @@ -66,7 +66,7 @@ void set_pcie_reset(void) pm_iowrite(0x94, byte); /* set the GPIO65 output enable and the value is 0 */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); word = pci_read_config16(sm_dev, 0x7e); word &= ~(1 << 0); word &= ~(1 << 4); @@ -106,7 +106,7 @@ static void set_gpio40_gfx(void) pm2_iowrite(0xf1, byte); /* access the smbus extended register */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); /* set the gfx to 1x16 lanes */ printk(BIOS_INFO, "Dev3 is not present. GFX Configuration is One x16 slot\n"); diff --git a/src/mainboard/gigabyte/ma785gmt/mainboard.c b/src/mainboard/gigabyte/ma785gmt/mainboard.c index 5949741b45..3b4edeece0 100644 --- a/src/mainboard/gigabyte/ma785gmt/mainboard.c +++ b/src/mainboard/gigabyte/ma785gmt/mainboard.c @@ -50,7 +50,7 @@ void set_pcie_dereset(void) pm_iowrite(0x94, byte); /* set the GPIO65 output enable and the value is 1 */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); word = pci_read_config16(sm_dev, 0x7e); word |= (1 << 0); word &= ~(1 << 4); @@ -76,7 +76,7 @@ void set_pcie_reset(void) pm_iowrite(0x94, byte); /* set the GPIO65 output enable and the value is 0 */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); word = pci_read_config16(sm_dev, 0x7e); word &= ~(1 << 0); word &= ~(1 << 4); @@ -92,7 +92,7 @@ int is_dev3_present(void) struct device *sm_dev; /* access the smbus extended register */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); /* put the GPIO68 output to tristate */ word = pci_read_config16(sm_dev, 0x7e); @@ -130,7 +130,7 @@ static void set_gpio40_gfx(void) pm2_iowrite(0xf1, byte); /* access the smbus extended register */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); /*if the dev3 is present, set the gfx to 2x8 lanes*/ /*otherwise set the gfx to 1x16 lanes*/ @@ -190,7 +190,7 @@ static void set_thermal_config(void) pm2_iowrite(0x42, byte); /* set GPIO 64 to input */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); word = pci_read_config16(sm_dev, 0x56); word |= 1 << 7; pci_write_config16(sm_dev, 0x56, word); diff --git a/src/mainboard/gigabyte/ma78gm/mainboard.c b/src/mainboard/gigabyte/ma78gm/mainboard.c index 6b0e229492..ff52b7b525 100644 --- a/src/mainboard/gigabyte/ma78gm/mainboard.c +++ b/src/mainboard/gigabyte/ma78gm/mainboard.c @@ -32,7 +32,7 @@ void set_pcie_dereset(void) u16 word; struct device *sm_dev; /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); word = pci_read_config16(sm_dev, 0xA8); word |= (1 << 0) | (1 << 2); /* Set Gpio6,4 as output */ @@ -45,7 +45,7 @@ void set_pcie_reset(void) u16 word; struct device *sm_dev; /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ - sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + sm_dev = pcidev_on_root(0x14, 0); word = pci_read_config16(sm_dev, 0xA8); word &= ~((1 << 0) | (1 << 2)); /* Set Gpio6,4 as output */ -- cgit v1.2.3