From 8ab989e31561cea0c6af5d5e242dd2be97bc73b4 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 30 Jul 2016 17:46:17 +0200 Subject: src/mainboard: Capitalize ROM, RAM, CPU and APIC Change-Id: Ia1f24d328a065a54975adde067df36c5751bff2d Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/15987 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c | 2 +- src/mainboard/gigabyte/ga_2761gxdk/romstage.c | 2 +- src/mainboard/gigabyte/m57sli/resourcemap.c | 2 +- src/mainboard/gigabyte/m57sli/romstage.c | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'src/mainboard/gigabyte') diff --git a/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c b/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c index 17b95e1491..35c54c8344 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/resourcemap.c @@ -265,7 +265,7 @@ static void setup_mb_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration region i */ -// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of cpu 0 --> Nvidia MCP55 */ +// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of CPU 0 --> Nvidia MCP55 */ PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index 35a5cb442f..8bc71a961a 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -193,5 +193,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); sis_init_stage2(); - post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now + post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now } diff --git a/src/mainboard/gigabyte/m57sli/resourcemap.c b/src/mainboard/gigabyte/m57sli/resourcemap.c index 17b95e1491..35c54c8344 100644 --- a/src/mainboard/gigabyte/m57sli/resourcemap.c +++ b/src/mainboard/gigabyte/m57sli/resourcemap.c @@ -265,7 +265,7 @@ static void setup_mb_resource_map(void) * [31:24] Bus Number Limit i * This field defines the highest bus number in configuration region i */ -// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of cpu 0 --> Nvidia MCP55 */ +// PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003, /* link 0 of CPU 0 --> Nvidia MCP55 */ PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index 67bf503baf..b1c849b9bb 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -199,5 +199,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); - post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now + post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now } -- cgit v1.2.3