From 17c577153042b6559bf7a9dca6ae9f644b18d770 Mon Sep 17 00:00:00 2001 From: Vagiz Trakhanov Date: Thu, 28 Sep 2017 14:21:54 +0000 Subject: superio/ite/common: Add temperature offset MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add a devicetree option to set temperature adjustment registers required for thermal diode sensors and PECI. However, this commit does not have the code needed to make PECI interface actually use these registers. It only applies to diodes. As a temporary workaround, one can set both THERMAL_DIODE and peci_tmpin to the same TMPIN, e.g. TMPIN3.mode="THERMAL_DIODE" and peci_tmpin="3". PECI, apparently, takes precedence over diode, so the adjustment register will be set and PECI activated. Or simply use the followup patch, which makes THERMAL_PECI a mode like THERMAL_DIODE. I don't have hardware to test THERMAL_DIODE mode, but in case of PECI, without this patch I had about -60°C on idle. Now, with offset 97, which was taken from vendor bios, PECI readings became reasonable 35°C. TEST=Set a temperature offset, then ensure that the value you set is reflected in /sys/class/hwmon/hwmon*/temp[1-3]_offset Change-Id: Ibce6809ca86b6c7c0c696676e309665fc57965d4 Signed-off-by: Vagiz Tarkhanov Reviewed-on: https://review.coreboot.org/21843 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb | 7 ++++--- src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb | 7 ++++--- 2 files changed, 8 insertions(+), 6 deletions(-) (limited to 'src/mainboard/gigabyte') diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb index acf743b18c..6bdc134b9a 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb @@ -110,9 +110,10 @@ chip northbridge/intel/i945 device pci 1f.0 on # LPC bridge ioapic_irq 2 INTA 0x10 chip superio/ite/it8718f # Super I/O - register "TMPIN1" = "THERMAL_RESISTOR" - register "TMPIN2" = "THERMAL_RESISTOR" - register "TMPIN3" = "THERMAL_DIODE" + register "TMPIN1.mode" = "THERMAL_RESISTOR" + register "TMPIN2.mode" = "THERMAL_RESISTOR" + register "TMPIN3.mode" = "THERMAL_DIODE" + register "TMPIN3.offset" = "0" register "ec.vin_mask" = "VIN_ALL" register "FAN1.mode" = "FAN_SMART_AUTOMATIC" diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb index 60004d25ea..39f790890e 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb @@ -82,9 +82,10 @@ chip northbridge/intel/x4x # Northbridge device pci 1f.0 on # ISA bridge subsystemid 0x1458 0x5001 chip superio/ite/it8718f # Super I/O - register "TMPIN1" = "THERMAL_RESISTOR" - register "TMPIN2" = "THERMAL_RESISTOR" - register "TMPIN3" = "THERMAL_DIODE" + register "TMPIN1.mode" = "THERMAL_RESISTOR" + register "TMPIN2.mode" = "THERMAL_RESISTOR" + register "TMPIN3.mode" = "THERMAL_DIODE" + register "TMPIN3.offset" = "0" register "ec.vin_mask" = "VIN7 | VIN4 | VIN3 | VIN2 | VIN1 | VIN0" register "FAN1.mode" = "FAN_SMART_AUTOMATIC" -- cgit v1.2.3