From 2e4dea663ce9f23f8cd925803b045259219d927d Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Mon, 12 May 2014 05:02:58 +1000 Subject: superio/ite/it8718f: Remove hard coding from romstage MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Make use of the ITE common Super I/O framework and there-by removing any hard coding of Super I/O base address. Change-Id: I14af89d2727d7c6bac0f9840043c430726297429 Signed-off-by: Edward O'Callaghan Reviewed-on: http://review.coreboot.org/5717 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/mainboard/gigabyte/ma785gm/romstage.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/mainboard/gigabyte/ma785gm/romstage.c') diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index 451cb7956c..62a9211c1d 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -47,6 +47,7 @@ #include "northbridge/amd/amdfam10/debug.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -95,7 +96,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_lpc_init(); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - it8718f_disable_reboot(); + it8718f_disable_reboot(GPIO_DEV); console_init(); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); -- cgit v1.2.3