From 669a7676354cab322873683868ff19d34c0cd302 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 2 Feb 2022 00:27:05 +0100 Subject: mb/gigabyte/ga-h61m-series: Add GA-H61M-DS2 Built from a mixture of autoport output, other variants, schematics and expert guesswork. I don't have this board, but the code has been tested by someone else and boots successfully (first try) with TianoCore. It's reasonable to assume most things work, as this board is very similar to the already-supported variants. Change-Id: I3d8df483e5573f77782b7d18b1410b391bfe387d Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/61541 Reviewed-by: Arthur Heymans Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- .../variants/ga-h61m-ds2/overridetree.cb | 56 ++++++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2/overridetree.cb (limited to 'src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2/overridetree.cb') diff --git a/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2/overridetree.cb b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2/overridetree.cb new file mode 100644 index 0000000000..3de795488f --- /dev/null +++ b/src/mainboard/gigabyte/ga-h61m-series/variants/ga-h61m-ds2/overridetree.cb @@ -0,0 +1,56 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/intel/sandybridge + device domain 0 on + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + + register "pcie_port_coalesce" = "true" + + device pci 1c.0 off end # RP #1 + device pci 1c.1 on end # RP #2: PCIe x1 Port (PCIEX1_1) + device pci 1c.2 off end # RP #3: + device pci 1c.3 off end # RP #4: + device pci 1c.4 on end # RP #5: Realtek RTL8111F GbE NIC + device pci 1c.5 on end # RP #6: PCIe x1 Port (PCIEX1_2) + + device pci 1f.0 on # LPC bridge + chip superio/ite/it8728f + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # COM1 + io 0x60 = 0x03f8 + irq 0x70 = 4 + end + device pnp 2e.2 off end # COM2 + device pnp 2e.3 off end # Parallel port + device pnp 2e.4 on # Environment Controller + io 0x60 = 0x0a30 + io 0x62 = 0x0a20 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + end + device pnp 2e.6 on end # Mouse + device pnp 2e.7 on # GPIO + irq 0x25 = 0x40 + irq 0x26 = 0xf7 + irq 0x27 = 0x10 + irq 0x2c = 0x80 + io 0x60 = 0x0000 + io 0x62 = 0x0a00 + io 0x64 = 0x0000 + irq 0x70 = 0x00 + irq 0x73 = 0x00 + irq 0xc1 = 0x37 + irq 0xcb = 0x00 + irq 0xf0 = 0x10 + irq 0xf1 = 0x42 + irq 0xf6 = 0x1c + end + device pnp 2e.a off end # CIR + end + end + end + end +end -- cgit v1.2.3