From ae317695e3f03d55fbba1805ff06e004383e67c8 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Sat, 20 Jul 2019 17:03:56 +0200 Subject: mb/,sb/intel/i82801gx: Merge `ide_legacy_combined` into `sata_mode` Functional changes were already done in 5eb81bed2e (sb/intel/i82801gx: Detect if the southbridge supports AHCI) but we forgot to update the `chip.h` and devicetrees. Change-Id: I0e25f54ead8f5bbc6041d31347038e800787b624 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/34462 Reviewed-by: Patrick Georgi Reviewed-by: Angel Pons Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb | 1 - 1 file changed, 1 deletion(-) (limited to 'src/mainboard/gigabyte/ga-g41m-es2l') diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb index d24eb5d6ac..7045dbf8e1 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb @@ -45,7 +45,6 @@ chip northbridge/intel/x4x # Northbridge register "pirqf_routing" = "0x0b" register "pirqg_routing" = "0x0b" register "pirqh_routing" = "0x0b" - register "ide_legacy_combined" = "0x0" # Combined mode broken register "ide_enable_primary" = "0x1" register "ide_enable_secondary" = "0x0" register "sata_ports_implemented" = "0x3" -- cgit v1.2.3