From fecf77770b8e68b9ef82021ca53c31db93736d93 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sat, 9 Nov 2019 14:19:04 +0100 Subject: sb/intel/i82801gx: Add common LPC decode code Generic LPC decode ranges can now be set from the devicetree. Change-Id: I1065ec770ad3a743286859efa39dca09ccb733a1 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36700 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Nico Huber Reviewed-by: Angel Pons --- src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | 15 +-------------- 1 file changed, 1 insertion(+), 14 deletions(-) (limited to 'src/mainboard/gigabyte/ga-g41m-es2l/romstage.c') diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index 8ba173eec6..fa69d122cb 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -98,19 +98,6 @@ static void mb_gpio_init(void) ich7_setup_cir(); } -static void ich7_enable_lpc(void) -{ - /* Disable Serial IRQ */ - pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0x00); - /* Decode range */ - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010); - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, - CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN | FDD_LPC_EN - | LPT_LPC_EN | COMA_LPC_EN | COMB_LPC_EN); - - pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x007c0291); -} - void mainboard_romstage_entry(void) { // ch0 ch1 @@ -119,7 +106,7 @@ void mainboard_romstage_entry(void) u8 s3_resume; /* Set southbridge and Super I/O GPIOs. */ - ich7_enable_lpc(); + i82801gx_lpc_setup(); mb_gpio_init(); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -- cgit v1.2.3