From cbe7a8e1008009c45551b56171da5df79a07fcce Mon Sep 17 00:00:00 2001 From: Damien Zammit Date: Wed, 19 Aug 2015 15:23:32 +1000 Subject: gigabyte/ga-g41m-es2l: Add mainboard Board uses x4x native raminit Board boots into Debian 8 with full graphics IRQ9: nobody cared, gets disabled (PIC needs IRQ settings?) VGA: - VGA native init works in grub with analog connector - Fails to boot with both channels of ram populated Change-Id: I7417813456817529b8cbaace45cefe47467d0a82 Signed-off-by: Damien Zammit Reviewed-on: https://review.coreboot.org/11306 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/mainboard/gigabyte/ga-g41m-es2l/acpi/ec.asl | 1 + .../gigabyte/ga-g41m-es2l/acpi/ich7_pci_irqs.asl | 34 +++++++++++ .../gigabyte/ga-g41m-es2l/acpi/platform.asl | 28 +++++++++ .../gigabyte/ga-g41m-es2l/acpi/superio.asl | 1 + .../gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl | 66 ++++++++++++++++++++++ 5 files changed, 130 insertions(+) create mode 100644 src/mainboard/gigabyte/ga-g41m-es2l/acpi/ec.asl create mode 100644 src/mainboard/gigabyte/ga-g41m-es2l/acpi/ich7_pci_irqs.asl create mode 100644 src/mainboard/gigabyte/ga-g41m-es2l/acpi/platform.asl create mode 100644 src/mainboard/gigabyte/ga-g41m-es2l/acpi/superio.asl create mode 100644 src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl (limited to 'src/mainboard/gigabyte/ga-g41m-es2l/acpi') diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/ec.asl b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/ec.asl new file mode 100644 index 0000000000..2997587d82 --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/ec.asl @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/ich7_pci_irqs.asl b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/ich7_pci_irqs.asl new file mode 100644 index 0000000000..0a69f3d3dc --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/ich7_pci_irqs.asl @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This is board specific information: + * IRQ routing for the 0:1e.0 PCI bridge of the ICH7 + */ + +If (PICM) { + Return (Package() { + Package() { 0x001effff, 0, 0, 17}, + Package() { 0x001effff, 1, 0, 20}, + Package() { 0x001effff, 2, 0, 16}, + Package() { 0x001effff, 3, 0, 16}, + }) +} Else { + Return (Package() { + Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0}, + Package() { 0x001effff, 2, \_SB.PCI0.LPCB.LNKA, 0}, + Package() { 0x001effff, 3, \_SB.PCI0.LPCB.LNKA, 0}, + }) +} diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/platform.asl b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/platform.asl new file mode 100644 index 0000000000..6c92a4ed47 --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/platform.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_PIC, 1) +{ + /* Remember the OS' IRQ routing choice. */ + Store(Arg0, PICM) +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) /* SMI Function */ + Store (0, TRP0) /* Generate trap */ + Return (SMIF) /* Return value of SMI handler */ +} diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/superio.asl b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/superio.asl new file mode 100644 index 0000000000..2997587d82 --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/superio.asl @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl new file mode 100644 index 0000000000..fdfe73d4a0 --- /dev/null +++ b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This is board specific information: IRQ routing for x4x */ + +/* PCI Interrupt Routing */ +Method(_PRT) +{ + If (PICM) { + Return (Package() { + /* Internal GFX */ + Package() { 0x0002ffff, 0, 0, 16 }, + /* High Definition Audio 0:1b.0 */ + Package() { 0x001bffff, 0, 0, 22 }, + /* PCIe Root Ports 0:1c.x */ + Package() { 0x001cffff, 0, 0, 16 }, + Package() { 0x001cffff, 1, 0, 17 }, + Package() { 0x001cffff, 2, 0, 18 }, + Package() { 0x001cffff, 3, 0, 19 }, + /* USB and EHCI 0:1d.x */ + Package() { 0x001dffff, 0, 0, 23 }, + Package() { 0x001dffff, 1, 0, 19 }, + Package() { 0x001dffff, 2, 0, 18 }, + Package() { 0x001dffff, 3, 0, 16 }, + Package() { 0x001dffff, 0, 0, 23 }, + /* SMBUS/SATA/PATA 0:1f.2, 0:1f.3 */ + Package() { 0x001fffff, 1, 0, 19 }, + Package() { 0x001fffff, 1, 0, 19 }, + Package() { 0x001fffff, 0, 0, 18 }, + }) + } Else { + Return (Package() { + /* Internal GFX */ + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + /* High Definition Audio 0:1b.0 */ + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + /* PCIe Root Ports 0:1c.x */ + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, + /* USB and EHCI 0:1d.x */ + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, + /* SMBUS/SATA/PATA 0:1f.2, 0:1f.3 */ + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, + }) + } +} -- cgit v1.2.3