From a8a9f34e9b7be8781c06c9d6fcc39f52bf31bd23 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 24 Dec 2017 08:11:13 +0100 Subject: sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tables Both southbridges need to be done at once since this southbridge code is used for different northbridges, which fails to compile when done separately. This needs an acpi_name functions in the northbridge code to be defined. TESTED on Intel DG43GT: show correct PIRQ ACPI entries in /sys/firmware/acpi/tables/SSDT. Change-Id: I286d251ddf8fcae27dd07011a1cd62d8f4847683 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/22981 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- .../gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl | 72 ---------------------- 1 file changed, 72 deletions(-) delete mode 100644 src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl (limited to 'src/mainboard/gigabyte/ga-g41m-es2l/acpi') diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl b/src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl deleted file mode 100644 index 46e8a4af5a..0000000000 --- a/src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl +++ /dev/null @@ -1,72 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Damien Zammit - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for x4x */ - -/* PCI Interrupt Routing */ -Method(_PRT) -{ - If (PICM) { - Return (Package() { - /* PEG */ - Package() { 0x0001ffff, 0, 0, 16 }, - /* Internal GFX */ - Package() { 0x0002ffff, 0, 0, 16 }, - /* High Definition Audio 0:1b.0 */ - Package() { 0x001bffff, 0, 0, 16 }, - /* PCIe Root Ports 0:1c.x */ - Package() { 0x001cffff, 0, 0, 16 }, - Package() { 0x001cffff, 1, 0, 17 }, - Package() { 0x001cffff, 2, 0, 18 }, - Package() { 0x001cffff, 3, 0, 19 }, - Package() { 0x001cffff, 0, 0, 16 }, - Package() { 0x001cffff, 1, 0, 17 }, - /* USB and EHCI 0:1d.x */ - Package() { 0x001dffff, 0, 0, 23 }, - Package() { 0x001dffff, 1, 0, 19 }, - Package() { 0x001dffff, 2, 0, 18 }, - Package() { 0x001dffff, 3, 0, 16 }, - /* SMBUS/SATA/PATA 0:1f.2, 0:1f.3 */ - Package() { 0x001fffff, 0, 0, 18 }, - Package() { 0x001fffff, 1, 0, 19 }, - Package() { 0x001fffff, 1, 0, 19 }, - }) - } Else { - Return (Package() { - /* PEG */ - Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - /* Internal GFX */ - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - /* High Definition Audio 0:1b.0 */ - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - /* PCIe Root Ports 0:1c.x */ - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - /* USB and EHCI 0:1d.x */ - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKH, 0 }, - Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, - /* SMBUS/SATA/PATA 0:1f.2, 0:1f.3 */ - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKD, 0 }, - }) - } -} -- cgit v1.2.3