From c583920a748fb8bd7999142433ad08641b06283d Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 12 Nov 2019 23:48:42 +0100 Subject: nb/intel/i945: Initialize console in bootblock Change-Id: Ic6ea158714998195614a63ee46a057f405de5616 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36796 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/mainboard/gigabyte/ga-945gcm-s2l/Makefile.inc | 2 + src/mainboard/gigabyte/ga-945gcm-s2l/early_init.c | 61 +++++++++++++++++++++++ src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c | 60 ---------------------- 3 files changed, 63 insertions(+), 60 deletions(-) create mode 100644 src/mainboard/gigabyte/ga-945gcm-s2l/early_init.c delete mode 100644 src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c (limited to 'src/mainboard/gigabyte/ga-945gcm-s2l') diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/Makefile.inc b/src/mainboard/gigabyte/ga-945gcm-s2l/Makefile.inc index f3d7e76263..a34f3f31c7 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/Makefile.inc +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/Makefile.inc @@ -1,2 +1,4 @@ ramstage-y += cstates.c romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/early_init.c b/src/mainboard/gigabyte/ga-945gcm-s2l/early_init.c new file mode 100644 index 0000000000..7b82059580 --- /dev/null +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/early_init.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2008 coresystems GmbH + * Copyright (C) 2016 Arthur Heymans arthur@aheymans.xyz + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) +#define EC_DEV PNP_DEV(0x2e, IT8718F_EC) +#define SUPERIO_DEV PNP_DEV(0x2e, 0) + +void bootblock_mainboard_early_init(void) +{ + /* Set default GPIOs on superio */ + ite_reg_write(GPIO_DEV, 0x25, 0x40); + ite_reg_write(GPIO_DEV, 0x26, 0x3f); + ite_reg_write(GPIO_DEV, 0x28, 0x41); + ite_reg_write(GPIO_DEV, 0x29, 0x88); + ite_reg_write(GPIO_DEV, 0x2c, 0x1c); + ite_reg_write(GPIO_DEV, 0x62, 0x08); + ite_kill_watchdog(GPIO_DEV); + ite_reg_write(GPIO_DEV, 0xb1, 0x01); + ite_reg_write(GPIO_DEV, 0xb8, 0x80); + ite_reg_write(GPIO_DEV, 0xbb, 0x40); + ite_reg_write(GPIO_DEV, 0xc0, 0x00); + ite_reg_write(GPIO_DEV, 0xc3, 0x00); + ite_reg_write(GPIO_DEV, 0xc8, 0x00); + ite_reg_write(GPIO_DEV, 0xcb, 0x00); + ite_reg_write(GPIO_DEV, 0xf6, 0x26); + ite_reg_write(GPIO_DEV, 0xfc, 0x01); + + ite_reg_write(EC_DEV, 0x70, 0x00); // Don't use IRQ9 + ite_reg_write(EC_DEV, 0x30, 0xff); // Enable + + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + /* Disable SIO reboot */ + ite_reg_write(GPIO_DEV, 0xEF, 0x7E); +} + +void mainboard_late_rcba_config(void) +{ + /* Enable PCIe Root Port Clock Gate */ + RCBA32(CG) = 0x00000001; +} diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c b/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c deleted file mode 100644 index 467a66f959..0000000000 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/romstage.c +++ /dev/null @@ -1,60 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2008 coresystems GmbH - * Copyright (C) 2016 Arthur Heymans arthur@aheymans.xyz - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) -#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) -#define EC_DEV PNP_DEV(0x2e, IT8718F_EC) -#define SUPERIO_DEV PNP_DEV(0x2e, 0) - -void mainboard_superio_config(void) -{ - /* Set default GPIOs on superio */ - ite_reg_write(GPIO_DEV, 0x25, 0x40); - ite_reg_write(GPIO_DEV, 0x26, 0x3f); - ite_reg_write(GPIO_DEV, 0x28, 0x41); - ite_reg_write(GPIO_DEV, 0x29, 0x88); - ite_reg_write(GPIO_DEV, 0x2c, 0x1c); - ite_reg_write(GPIO_DEV, 0x62, 0x08); - ite_kill_watchdog(GPIO_DEV); - ite_reg_write(GPIO_DEV, 0xb1, 0x01); - ite_reg_write(GPIO_DEV, 0xb8, 0x80); - ite_reg_write(GPIO_DEV, 0xbb, 0x40); - ite_reg_write(GPIO_DEV, 0xc0, 0x00); - ite_reg_write(GPIO_DEV, 0xc3, 0x00); - ite_reg_write(GPIO_DEV, 0xc8, 0x00); - ite_reg_write(GPIO_DEV, 0xcb, 0x00); - ite_reg_write(GPIO_DEV, 0xf6, 0x26); - ite_reg_write(GPIO_DEV, 0xfc, 0x01); - - ite_reg_write(EC_DEV, 0x70, 0x00); // Don't use IRQ9 - ite_reg_write(EC_DEV, 0x30, 0xff); // Enable - - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - /* Disable SIO reboot */ - ite_reg_write(GPIO_DEV, 0xEF, 0x7E); -} - -void mainboard_late_rcba_config(void) -{ - /* Enable PCIe Root Port Clock Gate */ - RCBA32(CG) = 0x00000001; -} -- cgit v1.2.3