From b451df2f400ba12fff440247330f8b57a93034bd Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 15 Aug 2017 20:59:09 +0200 Subject: mb/*/*/romstage.c: Clean up targets with i82801gx MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Things cleaned up in this patch: * Add macros for the GENx_DEC registers; * replace many magic numbers by macros; * remove many writes to DxxIP since they were 'setting' reset default values; * fix some comments about decode ranges. Change-Id: I9d6a0ff3d391947f611a2f3c65684f4ee57bc263 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/21065 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/mainboard/foxconn/g41s-k/romstage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/foxconn') diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c index ba07e45e99..5ea41ea194 100644 --- a/src/mainboard/foxconn/g41s-k/romstage.c +++ b/src/mainboard/foxconn/g41s-k/romstage.c @@ -78,7 +78,7 @@ static void ich7_enable_lpc(void) COMB_LPC_EN | COMA_LPC_EN); /* Decode 64 bytes at 0x0a00 to LPC for Super I/O EC and GPIO. */ - pci_write_config32(LPC_DEV, 0x84, 0x003c0a01); + pci_write_config32(LPC_DEV, GEN1_DEC, 0x003c0a01); } void mainboard_romstage_entry(unsigned long bist) -- cgit v1.2.3