From 2452afbe04584d48a9d76535f943c0cfc641aa19 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 11 Nov 2019 20:18:24 +0100 Subject: mb/*/*(ich7/x4x): Use common early southbridge init One functional change is that southbridge GPIO init is moved after console init. Change-Id: I53e6f177aadcdaa8c45593e0a8098e8d3c400d27 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36757 Reviewed-by: Angel Pons Reviewed-by: Patrick Georgi Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/mainboard/foxconn/g41s-k/romstage.c | 14 +------------- 1 file changed, 1 insertion(+), 13 deletions(-) (limited to 'src/mainboard/foxconn') diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c index f423c11378..45ff7e458e 100644 --- a/src/mainboard/foxconn/g41s-k/romstage.c +++ b/src/mainboard/foxconn/g41s-k/romstage.c @@ -20,7 +20,6 @@ #include #include #include -#include #include #include #include @@ -32,12 +31,6 @@ static void mb_lpc_setup(void) { - /* Set the value for GPIO base address register and enable GPIO. */ - pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); - pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); - /* Set up GPIOs on Super I/O. */ ite_reg_write(GPIO_DEV, 0x25, 0x01); ite_reg_write(GPIO_DEV, 0x26, 0x04); @@ -61,13 +54,7 @@ static void mb_lpc_setup(void) RCBA16(D30IR) = 0x3241; RCBA16(D29IR) = 0x0237; - /* Enable IOAPIC. */ - RCBA8(OIC) = 0x03; - RCBA8(OIC); - RCBA32(FD) |= FD_INTLAN; - - ich7_setup_cir(); } void mainboard_romstage_entry(void) @@ -92,6 +79,7 @@ void mainboard_romstage_entry(void) enable_smbus(); + i82801gx_early_init(); x4x_early_init(); s3_resume = southbridge_detect_s3_resume(); -- cgit v1.2.3