From 7843bd560e65b0a83e99b42bdd58dd6363656c56 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 11 Nov 2019 21:56:37 +0100 Subject: nb/intel/x4x: Move to C_ENVIRONMENT_BOOTBLOCK There is some overlap between things done in bootblock and romstage like setting BARs. Change-Id: Icd1de34c3b5c0f36f2a5249116d1829ee3956f38 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36759 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/mainboard/foxconn/g41s-k/Makefile.inc | 3 ++ src/mainboard/foxconn/g41s-k/early_init.c | 63 +++++++++++++++++++++++++++++++ src/mainboard/foxconn/g41s-k/romstage.c | 62 ------------------------------ 3 files changed, 66 insertions(+), 62 deletions(-) create mode 100644 src/mainboard/foxconn/g41s-k/early_init.c delete mode 100644 src/mainboard/foxconn/g41s-k/romstage.c (limited to 'src/mainboard/foxconn/g41s-k') diff --git a/src/mainboard/foxconn/g41s-k/Makefile.inc b/src/mainboard/foxconn/g41s-k/Makefile.inc index ca8de4d597..161c623eaa 100644 --- a/src/mainboard/foxconn/g41s-k/Makefile.inc +++ b/src/mainboard/foxconn/g41s-k/Makefile.inc @@ -1,6 +1,9 @@ ramstage-y += cstates.c romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c + ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/ diff --git a/src/mainboard/foxconn/g41s-k/early_init.c b/src/mainboard/foxconn/g41s-k/early_init.c new file mode 100644 index 0000000000..454b1ea0b0 --- /dev/null +++ b/src/mainboard/foxconn/g41s-k/early_init.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit + * Copyright (C) 2017 Arthur Heymans + * Copyright (C) 2017 Samuel Holland + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +#define SERIAL_DEV PNP_DEV(0x2e, IT8720F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8720F_GPIO) + +void bootblock_mainboard_early_init(void) +{ + /* Set up GPIOs on Super I/O. */ + ite_reg_write(GPIO_DEV, 0x25, 0x01); + ite_reg_write(GPIO_DEV, 0x26, 0x04); + ite_reg_write(GPIO_DEV, 0x27, 0x00); + ite_reg_write(GPIO_DEV, 0x28, 0x40); + ite_reg_write(GPIO_DEV, 0x29, 0x01); + ite_reg_write(GPIO_DEV, 0x73, 0x00); + ite_reg_write(GPIO_DEV, 0x74, 0x00); + ite_reg_write(GPIO_DEV, 0xb1, 0x04); + ite_reg_write(GPIO_DEV, 0xb8, 0x20); + ite_reg_write(GPIO_DEV, 0xbb, 0x01); + ite_reg_write(GPIO_DEV, 0xc0, 0x00); + ite_reg_write(GPIO_DEV, 0xc3, 0x01); + ite_reg_write(GPIO_DEV, 0xcb, 0x01); + ite_reg_write(GPIO_DEV, 0xf5, 0x28); + ite_reg_write(GPIO_DEV, 0xf6, 0x12); + ite_enable_3vsbsw(GPIO_DEV); + + /* Set up IRQ routing. */ + RCBA16(D31IR) = 0x0132; + RCBA16(D30IR) = 0x3241; + RCBA16(D29IR) = 0x0237; + + RCBA32(FD) |= FD_INTLAN; + + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} + +void mb_get_spd_map(u8 spd_map[4]) +{ + spd_map[0] = 0x50; + if (CONFIG(BOARD_FOXCONN_G41M)) + spd_map[2] = 0x52; +} diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c deleted file mode 100644 index b4bd77d78b..0000000000 --- a/src/mainboard/foxconn/g41s-k/romstage.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Damien Zammit - * Copyright (C) 2017 Arthur Heymans - * Copyright (C) 2017 Samuel Holland - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include - -#define SERIAL_DEV PNP_DEV(0x2e, IT8720F_SP1) -#define GPIO_DEV PNP_DEV(0x2e, IT8720F_GPIO) - -void mb_lpc_setup(void) -{ - /* Set up GPIOs on Super I/O. */ - ite_reg_write(GPIO_DEV, 0x25, 0x01); - ite_reg_write(GPIO_DEV, 0x26, 0x04); - ite_reg_write(GPIO_DEV, 0x27, 0x00); - ite_reg_write(GPIO_DEV, 0x28, 0x40); - ite_reg_write(GPIO_DEV, 0x29, 0x01); - ite_reg_write(GPIO_DEV, 0x73, 0x00); - ite_reg_write(GPIO_DEV, 0x74, 0x00); - ite_reg_write(GPIO_DEV, 0xb1, 0x04); - ite_reg_write(GPIO_DEV, 0xb8, 0x20); - ite_reg_write(GPIO_DEV, 0xbb, 0x01); - ite_reg_write(GPIO_DEV, 0xc0, 0x00); - ite_reg_write(GPIO_DEV, 0xc3, 0x01); - ite_reg_write(GPIO_DEV, 0xcb, 0x01); - ite_reg_write(GPIO_DEV, 0xf5, 0x28); - ite_reg_write(GPIO_DEV, 0xf6, 0x12); - ite_enable_3vsbsw(GPIO_DEV); - - /* Set up IRQ routing. */ - RCBA16(D31IR) = 0x0132; - RCBA16(D30IR) = 0x3241; - RCBA16(D29IR) = 0x0237; - - RCBA32(FD) |= FD_INTLAN; - - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -} - -void mb_get_spd_map(u8 spd_map[4]) -{ - spd_map[0] = 0x50; - if (CONFIG(BOARD_FOXCONN_G41M)) - spd_map[2] = 0x52; -} -- cgit v1.2.3