From fecf77770b8e68b9ef82021ca53c31db93736d93 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sat, 9 Nov 2019 14:19:04 +0100 Subject: sb/intel/i82801gx: Add common LPC decode code Generic LPC decode ranges can now be set from the devicetree. Change-Id: I1065ec770ad3a743286859efa39dca09ccb733a1 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36700 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Nico Huber Reviewed-by: Angel Pons --- src/mainboard/foxconn/g41s-k/devicetree.cb | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/mainboard/foxconn/g41s-k/devicetree.cb') diff --git a/src/mainboard/foxconn/g41s-k/devicetree.cb b/src/mainboard/foxconn/g41s-k/devicetree.cb index b196e24961..270d1355f1 100644 --- a/src/mainboard/foxconn/g41s-k/devicetree.cb +++ b/src/mainboard/foxconn/g41s-k/devicetree.cb @@ -49,6 +49,8 @@ chip northbridge/intel/x4x # Northbridge register "ide_enable_secondary" = "0x0" register "sata_ports_implemented" = "0x3" + register "gen1_dec" = "0x003c0a01" # Super I/O EC and GPIO + device pci 1b.0 on end # Audio device pci 1c.0 on end # PCIe 1 device pci 1c.1 on # PCIe 2 (NIC) -- cgit v1.2.3