From a0d9ad322fe603d4d4cbccda9c7edcfbf0b13409 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 3 Jan 2022 18:07:13 +0000 Subject: soc/intel/skl: Replace dt `HeciEnabled` by `HECI1 disable` config List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. 3. Make dt CSE PCI device `on` by default. 4. Mainboards set DISABLE_HECI1_AT_PRE_BOOT=y to make Heci1 function disable at pre-boot instead of the dt policy that uses `HeciEnabled = 0`. Mainboards that choose to make HECI1 enable during boot don't override `heci1 disable` config. Signed-off-by: Subrata Banik Change-Id: I5c13fe4a78be44403a81c28b1676aecc26c58607 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60722 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/facebook/monolith/Kconfig | 3 +++ src/mainboard/facebook/monolith/devicetree.cb | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) (limited to 'src/mainboard/facebook/monolith') diff --git a/src/mainboard/facebook/monolith/Kconfig b/src/mainboard/facebook/monolith/Kconfig index 50738f49d9..0fb05a1ef7 100644 --- a/src/mainboard/facebook/monolith/Kconfig +++ b/src/mainboard/facebook/monolith/Kconfig @@ -13,6 +13,9 @@ config BOARD_SPECIFIC_OPTIONS select INTEL_GMA_HAVE_VBT select VPD +config DISABLE_HECI1_AT_PRE_BOOT + default y + config CBFS_SIZE default 0x00900000 diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index 023ace9224..05bcc12257 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -36,7 +36,6 @@ chip soc/intel/skylake register "ScsEmmcHs400Enabled" = "1" register "SkipExtGfxScan" = "1" register "SaGv" = "SaGv_Enabled" - register "HeciEnabled" = "0" register "SataSalpSupport" = "1" register "SataPortsEnable" = "{ \ @@ -224,6 +223,7 @@ chip soc/intel/skylake device pci 14.0 on end # USB xHCI device pci 14.1 on end # USB xDCI (OTG) device pci 14.2 on end # Thermal Subsystem + device pci 16.0 on end # Management Engine Interface 1 device pci 17.0 on end # SATA device pci 1c.2 on end # PCI Express Port 3 x1 baseboard WWAN device pci 1c.5 on end # PCI Express Port 6 x1 baseboard i210 -- cgit v1.2.3