From 4f961371a5d48335e64623ee0840840b34fd25c3 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Fri, 27 Oct 2023 15:18:22 -0500 Subject: soc/intel/braswell: Unify DPTF enablement Currently, there are 3 separate settings for DPTF which are not always in sync: - the enabled/disabled state of the devicetree PCI device - the 'dptf_enable' register, which sets the ACPI device status via GNVS - the 'DptfDisable' register, which sets the FSP UPD of the same name To make things sane, drop the two chip registers, and set the GNVS variable and FSP UPD based on the enabled/disabled status of the DPTF PCI device in the mainboard's devicetree. TEST=build/boot google/cyan (edgar). Verify that the PCI and ACPI devices are present/enabled when DPTF is enabled in devicetree, and not present/disabled when disabled in devicetree. Change-Id: I8fc1b63eda0dc2e047d9cb1e11a02d41ab8b2ad7 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/78743 Tested-by: build bot (Jenkins) Reviewed-by: Martin L Roth --- src/mainboard/facebook/fbg1701/devicetree.cb | 1 - 1 file changed, 1 deletion(-) (limited to 'src/mainboard/facebook/fbg1701') diff --git a/src/mainboard/facebook/fbg1701/devicetree.cb b/src/mainboard/facebook/fbg1701/devicetree.cb index a77a6405f7..f0fd84becf 100644 --- a/src/mainboard/facebook/fbg1701/devicetree.cb +++ b/src/mainboard/facebook/fbg1701/devicetree.cb @@ -62,7 +62,6 @@ chip soc/intel/braswell register "ISPEnable" = "0" # Disable IUNIT register "ISPPciDevConfig" = "3" register "PcdSdDetectChk" = "0" # Disable SD card detect - register "DptfDisable" = "1" # LPE audio codec settings register "lpe_codec_clk_src" = "LPE_CLK_SRC_XTAL" # 19.2MHz clock -- cgit v1.2.3