From 710566093a504f0fecb641661c5379cad268189b Mon Sep 17 00:00:00 2001 From: Jonathan Neuschäfer Date: Fri, 10 Jun 2016 19:35:16 +0200 Subject: riscv-spike: Move coreboot to 0x80000000 (2GiB) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is where the RAM is (now), on RISC-V. We need to put coreboot.rom in RAM because Spike (at the moment) only supports loading code into the RAM, not into the boot ROM. Change-Id: I6c9b7cffe5fa414825491ee4ac0d2dad59a2d75c Signed-off-by: Jonathan Neuschäfer Reviewed-on: https://review.coreboot.org/15149 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/emulation/spike-riscv/memlayout.ld | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) (limited to 'src/mainboard/emulation') diff --git a/src/mainboard/emulation/spike-riscv/memlayout.ld b/src/mainboard/emulation/spike-riscv/memlayout.ld index 276483f336..8d35a64a9c 100644 --- a/src/mainboard/emulation/spike-riscv/memlayout.ld +++ b/src/mainboard/emulation/spike-riscv/memlayout.ld @@ -17,12 +17,14 @@ #include +#define START 0x80000000 + SECTIONS { - DRAM_START(0x0) - BOOTBLOCK(0x0, 64K) - STACK(8M, 64K) - ROMSTAGE(8M + 64K, 128K) - PRERAM_CBMEM_CONSOLE(8M + 192k, 8K) - RAMSTAGE(8M + 200K, 256K) + DRAM_START(START) + BOOTBLOCK(START, 64K) + STACK(START + 8M, 64K) + ROMSTAGE(START + 8M + 64K, 128K) + PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K) + RAMSTAGE(START + 8M + 200K, 256K) } -- cgit v1.2.3