From 0867062412dd4bfe5a556e5f3fd85ba5b682d79b Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Tue, 30 Jun 2009 15:17:49 +0000 Subject: This patch unifies the use of config options in v2 to all start with CONFIG_ It's basically done with the following script and some manual fixup: VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC` for VAR in $VARS; do find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \; done Signed-off-by: Stefan Reinauer Acked-by: Ronald G. Minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/emulation/qemu-x86/Config.lb | 50 ++++++------ src/mainboard/emulation/qemu-x86/Options.lb | 116 ++++++++++++++-------------- 2 files changed, 83 insertions(+), 83 deletions(-) (limited to 'src/mainboard/emulation') diff --git a/src/mainboard/emulation/qemu-x86/Config.lb b/src/mainboard/emulation/qemu-x86/Config.lb index cabcb2deeb..78e5936ffc 100644 --- a/src/mainboard/emulation/qemu-x86/Config.lb +++ b/src/mainboard/emulation/qemu-x86/Config.lb @@ -1,34 +1,34 @@ -## we don't use USE_DCACHE_RAM by default -default USE_DCACHE_RAM=0 +## we don't use CONFIG_USE_DCACHE_RAM by default +default CONFIG_USE_DCACHE_RAM=0 ## ## Compute the location and size of where this firmware image ## (coreboot plus bootloader) will live in the boot rom chip. ## -default ROM_SIZE = 256 * 1024 -default ROM_SECTION_SIZE = ROM_IMAGE_SIZE -default ROM_SECTION_OFFSET = 0 +default CONFIG_ROM_SIZE = 256 * 1024 +default CONFIG_ROM_SECTION_SIZE = CONFIG_ROM_IMAGE_SIZE +default CONFIG_ROM_SECTION_OFFSET = 0 ## ## Compute the start location and size size of ## The coreboot bootloader. ## -default PAYLOAD_SIZE = ( ROM_SIZE - ROM_IMAGE_SIZE ) -default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) +default CONFIG_PAYLOAD_SIZE = ( CONFIG_ROM_SIZE - CONFIG_ROM_IMAGE_SIZE ) +default CONFIG_ROM_PAYLOAD_START = (0xffffffff - CONFIG_ROM_SIZE + CONFIG_ROM_SECTION_OFFSET + 1) ## ## Compute where this copy of coreboot will start in the boot rom ## -default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) +default CONFIG_ROMBASE = ( CONFIG_ROM_PAYLOAD_START + CONFIG_PAYLOAD_SIZE ) ## ## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## -## XIP_ROM_SIZE must be a power of 2. -## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE +## CONFIG_XIP_ROM_SIZE must be a power of 2. +## CONFIG_XIP_ROM_BASE must be a multiple of CONFIG_XIP_ROM_SIZE ## -default XIP_ROM_SIZE=32*1024 -default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE ) +default CONFIG_XIP_ROM_SIZE=32*1024 +default CONFIG_XIP_ROM_BASE = ( CONFIG_ROMBASE + CONFIG_ROM_IMAGE_SIZE - CONFIG_XIP_ROM_SIZE ) ## ## Set all of the defaults for an x86 architecture @@ -41,15 +41,15 @@ arch i386 end ## driver mainboard.o -if HAVE_PIRQ_TABLE object irq_tables.o end +if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end #object reset.o -## ALL dependencies for USE_DCACHE_RAM go here. +## ALL dependencies for CONFIG_USE_DCACHE_RAM go here. ## That way, later, we can simply yank them if we wish. -## We include the old-fashioned entry code in the ! USE_DCACHE_RAM case. +## We include the old-fashioned entry code in the ! CONFIG_USE_DCACHE_RAM case. ## we do not use failover yet in this case. This is a work in progress. -if USE_DCACHE_RAM +if CONFIG_USE_DCACHE_RAM ## ## mainboardinit arch/i386/init/entry.S @@ -63,22 +63,22 @@ else ## Romcc output ## makerule ./failover.E - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./failover.inc - depends "$(MAINBOARD)/failover.c ../romcc" - action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@" + depends "$(CONFIG_MAINBOARD)/failover.c ../romcc" + action "../romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/failover.c -o $@" end makerule ./auto.E - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end makerule ./auto.inc - depends "$(MAINBOARD)/auto.c option_table.h ../romcc" - action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@" + depends "$(CONFIG_MAINBOARD)/auto.c option_table.h ../romcc" + action "../romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(CONFIG_MAINBOARD)/auto.c -o $@" end ## @@ -112,7 +112,7 @@ else ldscript /arch/i386/lib/id.lds ## -## end of USE_DCACHE_RAM bits. +## end of CONFIG_USE_DCACHE_RAM bits. ## end diff --git a/src/mainboard/emulation/qemu-x86/Options.lb b/src/mainboard/emulation/qemu-x86/Options.lb index fdb69ffc47..191c6c6a41 100644 --- a/src/mainboard/emulation/qemu-x86/Options.lb +++ b/src/mainboard/emulation/qemu-x86/Options.lb @@ -1,63 +1,63 @@ -uses HAVE_MP_TABLE -uses HAVE_PIRQ_TABLE -uses USE_FALLBACK_IMAGE -uses HAVE_FALLBACK_BOOT -uses HAVE_HARD_RESET -uses HAVE_OPTION_TABLE -uses USE_OPTION_TABLE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_HAVE_PIRQ_TABLE +uses CONFIG_USE_FALLBACK_IMAGE +uses CONFIG_HAVE_FALLBACK_BOOT +uses CONFIG_HAVE_HARD_RESET +uses CONFIG_HAVE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_COMPRESS uses CONFIG_COMPRESSED_PAYLOAD_NRV2B uses CONFIG_COMPRESSED_PAYLOAD_LZMA uses CONFIG_PRECOMPRESSED_PAYLOAD uses CONFIG_ROM_PAYLOAD -uses IRQ_SLOT_COUNT -uses MAINBOARD -uses MAINBOARD_VENDOR -uses MAINBOARD_PART_NUMBER +uses CONFIG_IRQ_SLOT_COUNT +uses CONFIG_MAINBOARD +uses CONFIG_MAINBOARD_VENDOR +uses CONFIG_MAINBOARD_PART_NUMBER uses COREBOOT_EXTRA_VERSION -uses ARCH -uses FALLBACK_SIZE -uses STACK_SIZE -uses HEAP_SIZE -uses ROM_SIZE -uses ROM_SECTION_SIZE -uses ROM_IMAGE_SIZE -uses ROM_SECTION_SIZE -uses ROM_SECTION_OFFSET +uses CONFIG_ARCH +uses CONFIG_FALLBACK_SIZE +uses CONFIG_STACK_SIZE +uses CONFIG_HEAP_SIZE +uses CONFIG_ROM_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_IMAGE_SIZE +uses CONFIG_ROM_SECTION_SIZE +uses CONFIG_ROM_SECTION_OFFSET uses CONFIG_ROM_PAYLOAD_START -uses PAYLOAD_SIZE -uses _ROMBASE -uses _RAMBASE -uses XIP_ROM_SIZE -uses XIP_ROM_BASE -uses HAVE_MP_TABLE -uses HAVE_HIGH_TABLES -uses CROSS_COMPILE +uses CONFIG_PAYLOAD_SIZE +uses CONFIG_ROMBASE +uses CONFIG_RAMBASE +uses CONFIG_XIP_ROM_SIZE +uses CONFIG_XIP_ROM_BASE +uses CONFIG_HAVE_MP_TABLE +uses CONFIG_HAVE_HIGH_TABLES +uses CONFIG_CROSS_COMPILE uses CC -uses HOSTCC -uses OBJCOPY +uses CONFIG_HOSTCC +uses CONFIG_OBJCOPY uses CONFIG_PCI_ROM_RUN uses CONFIG_PCI_OPTION_ROM_RUN_REALMODE uses CONFIG_CONSOLE_SERIAL8250 -uses USE_DCACHE_RAM -uses DCACHE_RAM_BASE -uses DCACHE_RAM_SIZE +uses CONFIG_USE_DCACHE_RAM +uses CONFIG_DCACHE_RAM_BASE +uses CONFIG_DCACHE_RAM_SIZE uses CONFIG_USE_INIT uses CONFIG_USE_PRINTK_IN_CAR -uses DEFAULT_CONSOLE_LOGLEVEL -uses MAXIMUM_CONSOLE_LOGLEVEL +uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL +uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL uses CONFIG_CBFS default CONFIG_CONSOLE_SERIAL8250=1 -default DEFAULT_CONSOLE_LOGLEVEL=8 -default MAXIMUM_CONSOLE_LOGLEVEL=8 +default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=8 +default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=8 default CONFIG_CBFS=1 -## ROM_SIZE is the size of boot ROM that this board will use. -default ROM_SIZE = 256*1024 +## CONFIG_ROM_SIZE is the size of boot ROM that this board will use. +default CONFIG_ROM_SIZE = 256*1024 ### ### Build options @@ -66,30 +66,30 @@ default ROM_SIZE = 256*1024 ## ## Build code for the fallback boot ## -default HAVE_FALLBACK_BOOT=1 +default CONFIG_HAVE_FALLBACK_BOOT=1 ## ## no MP table ## -default HAVE_MP_TABLE=0 +default CONFIG_HAVE_MP_TABLE=0 ## ## Build code to reset the motherboard from coreboot ## -default HAVE_HARD_RESET=0 +default CONFIG_HAVE_HARD_RESET=0 ## ## Build code to export a programmable irq routing table ## -default HAVE_PIRQ_TABLE=1 -default IRQ_SLOT_COUNT=6 +default CONFIG_HAVE_PIRQ_TABLE=1 +default CONFIG_IRQ_SLOT_COUNT=6 -default HAVE_HIGH_TABLES=1 +default CONFIG_HAVE_HIGH_TABLES=1 ## ## Build code to export a CMOS option table ## -default HAVE_OPTION_TABLE=1 +default CONFIG_HAVE_OPTION_TABLE=1 ## ## Option ROM init @@ -101,40 +101,40 @@ default CONFIG_PCI_OPTION_ROM_RUN_REALMODE=1 ### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. -default ROM_IMAGE_SIZE = 65536 -default FALLBACK_SIZE = ROM_IMAGE_SIZE +## CONFIG_ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. +default CONFIG_ROM_IMAGE_SIZE = 65536 +default CONFIG_FALLBACK_SIZE = CONFIG_ROM_IMAGE_SIZE ## ## Use a small 8K stack ## -default STACK_SIZE=0x2000 +default CONFIG_STACK_SIZE=0x2000 ## ## Use a small 16K heap ## -default HEAP_SIZE=0x4000 +default CONFIG_HEAP_SIZE=0x4000 ## ## Only use the option table in a normal image ## -#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE -default USE_OPTION_TABLE = 0 +#default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE +default CONFIG_USE_OPTION_TABLE = 0 -default _RAMBASE = 0x00004000 +default CONFIG_RAMBASE = 0x00004000 default CONFIG_ROM_PAYLOAD = 1 ## ## The default compiler ## -default CC="$(CROSS_COMPILE)gcc -m32" -default HOSTCC="gcc" +default CC="$(CONFIG_CROSS_COMPILE)gcc -m32" +default CONFIG_HOSTCC="gcc" ## ## known-good settings for qemu -default DCACHE_RAM_BASE=0x8f000 -default DCACHE_RAM_SIZE=0x1000 +default CONFIG_DCACHE_RAM_BASE=0x8f000 +default CONFIG_DCACHE_RAM_SIZE=0x1000 -- cgit v1.2.3