From baf27dbaeb1f6791ebfc416f2175507686bd88ac Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Wed, 2 Oct 2019 17:28:56 -0700 Subject: cbfs: Enable CBFS mcache on most chipsets This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is enabled by default. Some older chipsets with insufficient SRAM/CAR space still have it explicitly disabled. All others get the new section added to their memlayout... 8K seems like a sane default to start with. Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/38424 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/emulation/spike-riscv/memlayout.ld | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/mainboard/emulation/spike-riscv') diff --git a/src/mainboard/emulation/spike-riscv/memlayout.ld b/src/mainboard/emulation/spike-riscv/memlayout.ld index e08fd72b24..7ec489292c 100644 --- a/src/mainboard/emulation/spike-riscv/memlayout.ld +++ b/src/mainboard/emulation/spike-riscv/memlayout.ld @@ -12,7 +12,8 @@ SECTIONS BOOTBLOCK(START, 64K) STACK(START + 8M, 4K) FMAP_CACHE(START + 8M + 4K, 2K) - /* hole at (START + 8M + 6K, 58K) */ + CBFS_MCACHE(START + 8M + 6K, 8K) + /* hole at (START + 8M + 14K, 50K) */ ROMSTAGE(START + 8M + 64K, 128K) PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K) RAMSTAGE(START + 8M + 200K, 256K) -- cgit v1.2.3