From 99f2f113ec397dd042dcaa23c47123f3def19ebc Mon Sep 17 00:00:00 2001
From: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Date: Fri, 28 Oct 2016 00:25:02 +0200
Subject: riscv: Unify SBI call implementations under arch/riscv/
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Note that currently, traps are only handled by the trap handler
installed in the bootblock. The romstage and ramstage don't override it.

TEST=Booted emulation/spike-qemu and lowrisc/nexys4ddr with a linux
     payload. It worked as much as before (Linux didn't boot, but it
     made some successful SBI calls)

Change-Id: Icce96ab3f41ae0f34bd86e30f9ff17c30317854e
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/17057
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
---
 src/mainboard/emulation/spike-riscv/uart.c | 1 -
 1 file changed, 1 deletion(-)

(limited to 'src/mainboard/emulation/spike-riscv/uart.c')

diff --git a/src/mainboard/emulation/spike-riscv/uart.c b/src/mainboard/emulation/spike-riscv/uart.c
index 8513849f05..57647fee1d 100644
--- a/src/mainboard/emulation/spike-riscv/uart.c
+++ b/src/mainboard/emulation/spike-riscv/uart.c
@@ -17,7 +17,6 @@
 #include <console/uart.h>
 #include <arch/io.h>
 #include <boot/coreboot_tables.h>
-#include <spike_util.h>
 
 uintptr_t uart_platform_base(int idx)
 {
-- 
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