From 934ae21b52492c9c730dc5accd2900b32c5c1492 Mon Sep 17 00:00:00 2001 From: Philipp Hug Date: Wed, 4 Sep 2019 09:24:45 -0700 Subject: mb/emulation/qemu-riscv: Implement ipi using clint to enable smp in qemu/spike. TEST=Set MAX_CPUS=2 and run qemu with -smp 2 Signed-off-by: Philipp Hug Change-Id: I94fb25fad103e3cb5db676eb4caead11d54ae0ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/35246 Tested-by: build bot (Jenkins) Reviewed-by: Xiang Wang --- src/mainboard/emulation/spike-riscv/clint.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/mainboard/emulation/spike-riscv/clint.c') diff --git a/src/mainboard/emulation/spike-riscv/clint.c b/src/mainboard/emulation/spike-riscv/clint.c index 7ad3f5a7af..c39e05831c 100644 --- a/src/mainboard/emulation/spike-riscv/clint.c +++ b/src/mainboard/emulation/spike-riscv/clint.c @@ -14,6 +14,7 @@ */ #include +#include #define SPIKE_CLINT_BASE 0x02000000 @@ -24,3 +25,8 @@ void mtime_init(void) HLS()->time = (uint64_t *)(SPIKE_CLINT_BASE + 0xbff8); HLS()->timecmp = (uint64_t *)(SPIKE_CLINT_BASE + 0x4000 + 8 * hart_id); } + +void set_msip(int hartid, int val) +{ + write32((void *)(SPIKE_CLINT_BASE + 4 * (uintptr_t)hartid), !!val); +} -- cgit v1.2.3