From 0588d19abef62dad63a7794a37bdd6a71c526d9e Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Wed, 12 Aug 2009 15:00:51 +0000 Subject: Kconfig! Works on Kontron, qemu, and serengeti. Signed-off-by: Patrick Georgi tested on abuild only. Acked-by: Ronald G. Minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/emulation/qemu-x86/Makefile.inc | 21 +++++++++++++++++++++ src/mainboard/emulation/qemu-x86/devicetree.cb | 15 +++++++++++++++ 2 files changed, 36 insertions(+) create mode 100644 src/mainboard/emulation/qemu-x86/Makefile.inc create mode 100644 src/mainboard/emulation/qemu-x86/devicetree.cb (limited to 'src/mainboard/emulation/qemu-x86') diff --git a/src/mainboard/emulation/qemu-x86/Makefile.inc b/src/mainboard/emulation/qemu-x86/Makefile.inc new file mode 100644 index 0000000000..1985b2e8b3 --- /dev/null +++ b/src/mainboard/emulation/qemu-x86/Makefile.inc @@ -0,0 +1,21 @@ +initobj-y += crt0.o +crt0-y += ../../../../src/cpu/x86/16bit/entry16.inc +crt0-y += ../../../../src/cpu/x86/32bit/entry32.inc +crt0-y += ../../../../src/cpu/x86/16bit/reset16.inc +crt0-y += ../../../../src/arch/i386/lib/id.inc +crt0-y += auto.inc + +obj-y += mainboard.o + +ldscript-y += ../../../../src/arch/i386/init/ldscript_fallback_cbfs.lb +ldscript-y += ../../../../src/cpu/x86/16bit/entry16.lds +ldscript-y += ../../../../src/cpu/x86/32bit/entry32.lds +ldscript-y += ../../../../src/cpu/x86/16bit/reset16.lds +ldscript-y += ../../../../src/arch/i386/lib/id.lds + +ifdef POST_EVALUATION + +$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(obj)/romcc $(src)/mainboard/$(MAINBOARDDIR)/auto.c $(obj)/option_table.h + $(obj)/romcc -mcpu=i386 -O $(INCLUDES) $(src)/mainboard/$(MAINBOARDDIR)/auto.c -o $@ + +endif diff --git a/src/mainboard/emulation/qemu-x86/devicetree.cb b/src/mainboard/emulation/qemu-x86/devicetree.cb new file mode 100644 index 0000000000..745ff189d1 --- /dev/null +++ b/src/mainboard/emulation/qemu-x86/devicetree.cb @@ -0,0 +1,15 @@ +chip cpu/emulation/qemu-x86 + device pci_domain 0 on + device pci 0.0 on end + + chip southbridge/intel/i82371eb # southbridge + device pci 01.0 on end + device pci 01.1 on end + register "ide0_enable" = "1" + register "ide1_enable" = "1" + end + +# register "com1" = "{1}" +# register "com1" = "{1, 0, 0x3f8, 4}" + end +end -- cgit v1.2.3