From baf27dbaeb1f6791ebfc416f2175507686bd88ac Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Wed, 2 Oct 2019 17:28:56 -0700 Subject: cbfs: Enable CBFS mcache on most chipsets This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is enabled by default. Some older chipsets with insufficient SRAM/CAR space still have it explicitly disabled. All others get the new section added to their memlayout... 8K seems like a sane default to start with. Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/38424 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/emulation/qemu-riscv/memlayout.ld | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mainboard/emulation/qemu-riscv') diff --git a/src/mainboard/emulation/qemu-riscv/memlayout.ld b/src/mainboard/emulation/qemu-riscv/memlayout.ld index cfa0513520..96ab74c516 100644 --- a/src/mainboard/emulation/qemu-riscv/memlayout.ld +++ b/src/mainboard/emulation/qemu-riscv/memlayout.ld @@ -25,6 +25,7 @@ SECTIONS #endif PRERAM_CBMEM_CONSOLE(STAGES_START + 128K, 8K) FMAP_CACHE(STAGES_START + 136K, 2K) + CBFS_MCACHE(STAGES_START + 138K, 8K) RAMSTAGE(STAGES_START + 200K, 16M) STACK(STAGES_START + 200K + 16M, 4K) } -- cgit v1.2.3