From e0e784a456c4d64e5e88ce578371fe6c538db559 Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Wed, 26 Nov 2014 19:25:47 +0000 Subject: Add UCB RISCV support for architecture, soc, and emulation mainboard.. Works in the RISCV version of QEMU. Note that the lzmadecode is so unclean that it needs a lot of work. A cleanup is in progress. We decided in Prague to do this as one thing, because it forms a nice case study of the bare minimum you need to add to get a new architecture going in qemu. Change-Id: If5af15c3a70733d219973e0d032746f8ab027e4d Signed-off-by: Ronald G. Minnich Reviewed-on: http://review.coreboot.org/7584 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/mainboard/emulation/qemu-riscv/devicetree.cb | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 src/mainboard/emulation/qemu-riscv/devicetree.cb (limited to 'src/mainboard/emulation/qemu-riscv/devicetree.cb') diff --git a/src/mainboard/emulation/qemu-riscv/devicetree.cb b/src/mainboard/emulation/qemu-riscv/devicetree.cb new file mode 100644 index 0000000000..e3ce08829e --- /dev/null +++ b/src/mainboard/emulation/qemu-riscv/devicetree.cb @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2014 Google, Inc. +## +## This software is licensed under the terms of the GNU General Public +## License version 2, as published by the Free Software Foundation, and +## may be copied, distributed, and modified under those terms. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. + +chip soc/ucb/riscv + device cpu_cluster 0 on end + chip drivers/generic/generic # I2C0 controller + device i2c 6 on end # Fake component for testing + end +end -- cgit v1.2.3