From 99f2f113ec397dd042dcaa23c47123f3def19ebc Mon Sep 17 00:00:00 2001 From: Jonathan Neuschäfer Date: Fri, 28 Oct 2016 00:25:02 +0200 Subject: riscv: Unify SBI call implementations under arch/riscv/ MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Note that currently, traps are only handled by the trap handler installed in the bootblock. The romstage and ramstage don't override it. TEST=Booted emulation/spike-qemu and lowrisc/nexys4ddr with a linux payload. It worked as much as before (Linux didn't boot, but it made some successful SBI calls) Change-Id: Icce96ab3f41ae0f34bd86e30f9ff17c30317854e Signed-off-by: Jonathan Neuschäfer Reviewed-on: https://review.coreboot.org/17057 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth Reviewed-by: Ronald G. Minnich --- src/mainboard/emulation/qemu-riscv/Makefile.inc | 3 --- 1 file changed, 3 deletions(-) (limited to 'src/mainboard/emulation/qemu-riscv/Makefile.inc') diff --git a/src/mainboard/emulation/qemu-riscv/Makefile.inc b/src/mainboard/emulation/qemu-riscv/Makefile.inc index 4fbe401944..36f1fca58c 100644 --- a/src/mainboard/emulation/qemu-riscv/Makefile.inc +++ b/src/mainboard/emulation/qemu-riscv/Makefile.inc @@ -13,14 +13,11 @@ ## GNU General Public License for more details. bootblock-y += uart.c -bootblock-y += qemu_util.c bootblock-y += rom_media.c romstage-y += romstage.c -romstage-y += qemu_util.c romstage-y += uart.c romstage-y += rom_media.c ramstage-y += uart.c -ramstage-y += qemu_util.c ramstage-y += rom_media.c bootblock-y += memlayout.ld -- cgit v1.2.3