From 042772a6bd66cd09add08da40785406e34e92d0a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= Date: Fri, 30 Nov 2018 00:06:51 +0100 Subject: mb/emulation/spike-riscv: Implement mtime_init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch lets spike boot to "Payload not loaded" again. Because soc/ucb/riscv/ does not represent a real SoC, but is a dummy directory for emulators, and different emulators might have different memory maps, I moved mtime_init to the mainboard-specific directories for Spike and QEMU. Change-Id: I080f7f81df752e25478bd277637bf894bbee4cb2 Signed-off-by: Jonathan Neuschäfer Reviewed-on: https://review.coreboot.org/c/28873 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Hug --- src/mainboard/emulation/qemu-riscv/Makefile.inc | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/mainboard/emulation/qemu-riscv/Makefile.inc') diff --git a/src/mainboard/emulation/qemu-riscv/Makefile.inc b/src/mainboard/emulation/qemu-riscv/Makefile.inc index 36f1fca58c..1d882acc63 100644 --- a/src/mainboard/emulation/qemu-riscv/Makefile.inc +++ b/src/mainboard/emulation/qemu-riscv/Makefile.inc @@ -14,11 +14,15 @@ bootblock-y += uart.c bootblock-y += rom_media.c +bootblock-y += mtime.c + romstage-y += romstage.c romstage-y += uart.c romstage-y += rom_media.c + ramstage-y += uart.c ramstage-y += rom_media.c +ramstage-y += mtime.c bootblock-y += memlayout.ld romstage-y += memlayout.ld -- cgit v1.2.3