From c700829cd3657f1840be581760ca0a2f13226238 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Sat, 23 Sep 2017 19:12:38 +0300 Subject: AGESA f14: Drop PlatformGnbPcieComplex.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These were OEM configurations hidden inside a header file, notation was already dropped for f15tb and f16kb. Change-Id: Id64fa861fd516e9f7cae9eba9b8145e033fe9bdd Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/21650 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Marc Jones --- src/mainboard/elmex/pcm205400/OemCustomize.c | 11 ++- .../elmex/pcm205400/PlatformGnbPcieComplex.h | 100 --------------------- 2 files changed, 5 insertions(+), 106 deletions(-) delete mode 100644 src/mainboard/elmex/pcm205400/PlatformGnbPcieComplex.h (limited to 'src/mainboard/elmex/pcm205400') diff --git a/src/mainboard/elmex/pcm205400/OemCustomize.c b/src/mainboard/elmex/pcm205400/OemCustomize.c index 93adb34165..05f2807ece 100644 --- a/src/mainboard/elmex/pcm205400/OemCustomize.c +++ b/src/mainboard/elmex/pcm205400/OemCustomize.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include "PlatformGnbPcieComplex.h" #include #include @@ -24,31 +23,31 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), - PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT4_PORT_PRESENT, GNB_GPP_PORT4_CHANNEL_TYPE, 4, GNB_GPP_PORT4_HOTPLUG_SUPPORT, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_SPEED_MODE, GNB_GPP_PORT4_LINK_ASPM, 46) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 46) }, // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT5_PORT_PRESENT, GNB_GPP_PORT5_CHANNEL_TYPE, 5, GNB_GPP_PORT5_HOTPLUG_SUPPORT, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_SPEED_MODE, GNB_GPP_PORT5_LINK_ASPM, 46) + PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 46) }, // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT6_PORT_PRESENT, GNB_GPP_PORT6_CHANNEL_TYPE, 6, GNB_GPP_PORT6_HOTPLUG_SUPPORT, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_SPEED_MODE, GNB_GPP_PORT6_LINK_ASPM, 46) + PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 46) }, // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT7_PORT_PRESENT, GNB_GPP_PORT7_CHANNEL_TYPE, 7, GNB_GPP_PORT7_HOTPLUG_SUPPORT, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_SPEED_MODE, GNB_GPP_PORT7_LINK_ASPM, 0) + PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0) }, // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER(GNB_GPP_PORT8_PORT_PRESENT, GNB_GPP_PORT8_CHANNEL_TYPE, 8, GNB_GPP_PORT8_HOTPLUG_SUPPORT, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_SPEED_MODE, GNB_GPP_PORT8_LINK_ASPM, 0) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0) } }; diff --git a/src/mainboard/elmex/pcm205400/PlatformGnbPcieComplex.h b/src/mainboard/elmex/pcm205400/PlatformGnbPcieComplex.h deleted file mode 100644 index 0bea8970e9..0000000000 --- a/src/mainboard/elmex/pcm205400/PlatformGnbPcieComplex.h +++ /dev/null @@ -1,100 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H -#define _PLATFORM_GNB_PCIE_COMPLEX_H - -/* - * GNB GPP Port4 - * GNB_GPP_PORT4_PORT_PRESENT 0:Disable 1:Enable - * GNB_GPP_PORT4_SPEED_MODE 0:Auto 1:GEN1 2:GEN2 - * GNB_GPP_PORT4_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1 - * GNB_GPP_PORT4_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db) - * 2:Half-swing(0db) 3:Half-swing(-3.5db) - * 4:extended length(-6db) 5:extended length(-8db) - * GNB_GPP_PORT4_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced - */ -#define GNB_GPP_PORT4_PORT_PRESENT 1 -#define GNB_GPP_PORT4_SPEED_MODE 2 -#define GNB_GPP_PORT4_LINK_ASPM 3 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 -#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 - -/* - * GNB GPP Port5 - * GNB_GPP_PORT5_PORT_PRESENT 0:Disable 1:Enable - * GNB_GPP_PORT5_SPEED_MODE 0:Auto 1:GEN1 2:GEN2 - * GNB_GPP_PORT5_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1 - * GNB_GPP_PORT5_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db) - * 2:Half-swing(0db) 3:Half-swing(-3.5db) - * 4:extended length(-6db) 5:extended length(-8db) - * GNB_GPP_PORT5_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced - */ -#define GNB_GPP_PORT5_PORT_PRESENT 0 -#define GNB_GPP_PORT5_SPEED_MODE 2 -#define GNB_GPP_PORT5_LINK_ASPM 3 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 -#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 - -/* - * GNB GPP Port6 - * GNB_GPP_PORT6_PORT_PRESENT 0:Disable 1:Enable - * GNB_GPP_PORT6_SPEED_MODE 0:Auto 1:GEN1 2:GEN2 - * GNB_GPP_PORT6_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1 - * GNB_GPP_PORT6_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db) - * 2:Half-swing(0db) 3:Half-swing(-3.5db) - * 4:extended length(-6db) 5:extended length(-8db) - * GNB_GPP_PORT6_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced - */ -#define GNB_GPP_PORT6_PORT_PRESENT 0 -#define GNB_GPP_PORT6_SPEED_MODE 2 -#define GNB_GPP_PORT6_LINK_ASPM 3 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 -#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 - -/* - * GNB GPP Port7 - * GNB_GPP_PORT7_PORT_PRESENT 0:Disable 1:Enable - * GNB_GPP_PORT7_SPEED_MODE 0:Auto 1:GEN1 2:GEN2 - * GNB_GPP_PORT7_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1 - * GNB_GPP_PORT7_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db) - * 2:Half-swing(0db) 3:Half-swing(-3.5db) - * 4:extended length(-6db) 5:extended length(-8db) - * GNB_GPP_PORT7_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced - */ -#define GNB_GPP_PORT7_PORT_PRESENT 0 -#define GNB_GPP_PORT7_SPEED_MODE 2 -#define GNB_GPP_PORT7_LINK_ASPM 3 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 -#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 - -/* - * GNB GPP Port8 - * GNB_GPP_PORT8_PORT_PRESENT 0:Disable 1:Enable - * GNB_GPP_PORT8_SPEED_MODE 0:Auto 1:GEN1 2:GEN2 - * GNB_GPP_PORT8_LINK_ASPM 0:Disable 1:L0s 2:L1 3:L0s+L1 - * GNB_GPP_PORT8_CHANNEL_TYPE 0:LowLoss(-3.5db) 1:HighLoss(-6db) - * 2:Half-swing(0db) 3:Half-swing(-3.5db) - * 4:extended length(-6db) 5:extended length(-8db) - * GNB_GPP_PORT8_HOTPLUG_SUPPORT 0:Disable 1:Basic 3:Enhanced - */ -#define GNB_GPP_PORT8_PORT_PRESENT 1 -#define GNB_GPP_PORT8_SPEED_MODE 2 -#define GNB_GPP_PORT8_LINK_ASPM 3 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 -#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 - - -#endif //_PLATFORM_GNB_PCIE_COMPLEX_H -- cgit v1.2.3