From ab50d62ea6867712eca79e9f0770d6ac35f72ce1 Mon Sep 17 00:00:00 2001 From: Uwe Hermann Date: Wed, 13 Oct 2010 08:21:44 +0000 Subject: Convert all Intel i810 boards to CAR. - Drop "select ROMCC" from the boards, as well as early_mtrr stuff. - Add "select CACHE_AS_RAM" to socket_PGA370/Kconfig, as well as the usual DCACHE_RAM_BASE and DCACHE_RAM_SIZE variables. - In socket_PGA370/Makefile.inc add: cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc - Other smaller related fixes. Abuild-tested and boot-tested on MSI MS-6178. Signed-off-by: Uwe Hermann Acked-by: Peter Stuge git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5949 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/ecs/p6iwp-fe/Kconfig | 1 - src/mainboard/ecs/p6iwp-fe/romstage.c | 22 ++-------------------- 2 files changed, 2 insertions(+), 21 deletions(-) (limited to 'src/mainboard/ecs') diff --git a/src/mainboard/ecs/p6iwp-fe/Kconfig b/src/mainboard/ecs/p6iwp-fe/Kconfig index eecae4d4bd..7d377f4717 100644 --- a/src/mainboard/ecs/p6iwp-fe/Kconfig +++ b/src/mainboard/ecs/p6iwp-fe/Kconfig @@ -26,7 +26,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select NORTHBRIDGE_INTEL_I82810 select SOUTHBRIDGE_INTEL_I82801AX select SUPERIO_ITE_IT8712F - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512 diff --git a/src/mainboard/ecs/p6iwp-fe/romstage.c b/src/mainboard/ecs/p6iwp-fe/romstage.c index f84ff465c9..b899d938af 100644 --- a/src/mainboard/ecs/p6iwp-fe/romstage.c +++ b/src/mainboard/ecs/p6iwp-fe/romstage.c @@ -27,37 +27,21 @@ #include #include #include -#include "lib/ramtest.c" #include "southbridge/intel/i82801ax/i82801ax_early_smbus.c" #include "northbridge/intel/i82810/raminit.h" #include "lib/debug.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "superio/ite/it8712f/it8712f_early_serial.c" - -static inline int spd_read_byte(unsigned int device, unsigned int address) -{ - return smbus_read_byte(device, address); -} - #include "northbridge/intel/i82810/raminit.c" #include "northbridge/intel/i82810/debug.c" +#include -/* Early mainboard specific GPIO setup. */ -static void mb_gpio_init(void) +void main(unsigned long bist) { -} - -static void main(unsigned long bist) -{ - if (bist == 0) - early_mtrr_init(); - it8712f_24mhz_clkin(); it8712f_enable_serial(0, CONFIG_TTYS0_BASE); // Does not use its 1st parameter - mb_gpio_init(); uart_init(); console_init(); report_bist_failure(bist); @@ -67,6 +51,4 @@ static void main(unsigned long bist) sdram_set_spd_registers(); sdram_enable(); dump_spd_registers(); - /* ram_check(0, 640 * 1024); */ } - -- cgit v1.2.3