From 38f147ed3d9fdd6bfb23d7226f6fdd3fc5db53d0 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Mon, 8 Feb 2010 12:20:50 +0000 Subject: janitor task: unify and cleanup naming. cache_as_ram_auto.c and auto.c are both called "romstage.c" now. Signed-off-by: Stefan Reinauer Acked-by: Patrick Georgi git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5092 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/digitallogic/adl855pc/auto.c | 143 ----------- src/mainboard/digitallogic/adl855pc/romstage.c | 143 +++++++++++ src/mainboard/digitallogic/msm586seg/auto.c | 281 --------------------- src/mainboard/digitallogic/msm586seg/romstage.c | 281 +++++++++++++++++++++ src/mainboard/digitallogic/msm800sev/Makefile.inc | 6 +- src/mainboard/digitallogic/msm800sev/auto.c | 138 ---------- .../digitallogic/msm800sev/cache_as_ram_auto.c | 120 --------- src/mainboard/digitallogic/msm800sev/romstage.c | 120 +++++++++ 8 files changed, 547 insertions(+), 685 deletions(-) delete mode 100644 src/mainboard/digitallogic/adl855pc/auto.c create mode 100644 src/mainboard/digitallogic/adl855pc/romstage.c delete mode 100644 src/mainboard/digitallogic/msm586seg/auto.c create mode 100644 src/mainboard/digitallogic/msm586seg/romstage.c delete mode 100644 src/mainboard/digitallogic/msm800sev/auto.c delete mode 100644 src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c create mode 100644 src/mainboard/digitallogic/msm800sev/romstage.c (limited to 'src/mainboard/digitallogic') diff --git a/src/mainboard/digitallogic/adl855pc/auto.c b/src/mainboard/digitallogic/adl855pc/auto.c deleted file mode 100644 index cbd8bb0488..0000000000 --- a/src/mainboard/digitallogic/adl855pc/auto.c +++ /dev/null @@ -1,143 +0,0 @@ -#define ASSEMBLY 1 -#define __PRE_RAM__ -#define ASM_CONSOLE_LOGLEVEL 8 -#include -#include -#include -#include -#include -#if 0 -#include -#endif -#include -//#include "option_table.h" -#include -#include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "arch/i386/lib/console.c" -#include "lib/ramtest.c" -#include "southbridge/intel/i82801dbm/i82801dbm_early_smbus.c" -#include "northbridge/intel/i855pm/raminit.h" - -#if 0 -#include "cpu/p6/apic_timer.c" -#include "lib/delay.c" -#endif - -#include "cpu/x86/lapic/boot_cpu.c" -#include "northbridge/intel/i855pm/debug.c" -#include "superio/winbond/w83627hf/w83627hf_early_serial.c" -#include "cpu/x86/mtrr/earlymtrr.c" -#include "cpu/x86/bist.h" - -#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) - -static void hard_reset(void) -{ - outb(0x0e, 0x0cf9); -} - -static void memreset_setup(void) -{ -} - -static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} - - - -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -#include "northbridge/intel/i855pm/raminit.c" -#include "northbridge/intel/i855pm/reset_test.c" -#include "lib/generic_sdram.c" - -static void main(unsigned long bist) -{ - static const struct mem_controller memctrl[] = { - { - .d0 = PCI_DEV(0, 0, 1), - .channel0 = { (0xa<<3)|0, 0 }, - }, - }; - - if (bist == 0) { - early_mtrr_init(); -#if 0 - enable_lapic(); - init_timer(); -#endif - } - - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - uart_init(); - console_init(); - - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - - -#if 0 - print_pci_devices(); -#endif - - if(!bios_reset_detected()) { - enable_smbus(); -#if 0 - dump_spd_registers(&memctrl[0]); - // dump_smbus_registers(); -#endif - - - memreset_setup(); - - sdram_initialize(ARRAY_SIZE(memctrl), memctrl); - - } -#if 0 - else { - /* clear memory 1meg */ - __asm__ volatile( - "1: \n\t" - "movl %0, %%fs:(%1)\n\t" - "addl $4,%1\n\t" - "subl $4,%2\n\t" - "jnz 1b\n\t" - : - : "a" (0), "D" (0), "c" (1024*1024) - ); - - } -#endif - -#if 0 - dump_pci_devices(); -#endif -#if 0 - dump_pci_device(PCI_DEV(0, 0, 0)); -#endif - -/* -#if 0 - ram_check(0x00000000, msr.lo+(msr.hi<<32)); -#else -#if 0 - // Check 16MB of memory @ 0 - ram_check(0x00000000, 0x01000000); -#else - // Check 16MB of memory @ 2GB - ram_check(0x80000000, 0x81000000); -#endif -#endif -*/ -} diff --git a/src/mainboard/digitallogic/adl855pc/romstage.c b/src/mainboard/digitallogic/adl855pc/romstage.c new file mode 100644 index 0000000000..cbd8bb0488 --- /dev/null +++ b/src/mainboard/digitallogic/adl855pc/romstage.c @@ -0,0 +1,143 @@ +#define ASSEMBLY 1 +#define __PRE_RAM__ +#define ASM_CONSOLE_LOGLEVEL 8 +#include +#include +#include +#include +#include +#if 0 +#include +#endif +#include +//#include "option_table.h" +#include +#include "pc80/mc146818rtc_early.c" +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "lib/ramtest.c" +#include "southbridge/intel/i82801dbm/i82801dbm_early_smbus.c" +#include "northbridge/intel/i855pm/raminit.h" + +#if 0 +#include "cpu/p6/apic_timer.c" +#include "lib/delay.c" +#endif + +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/intel/i855pm/debug.c" +#include "superio/winbond/w83627hf/w83627hf_early_serial.c" +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" + +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) + +static void hard_reset(void) +{ + outb(0x0e, 0x0cf9); +} + +static void memreset_setup(void) +{ +} + +static void memreset(int controllers, const struct mem_controller *ctrl) +{ +} + + + +static inline void activate_spd_rom(const struct mem_controller *ctrl) +{ + /* nothing to do */ +} + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/intel/i855pm/raminit.c" +#include "northbridge/intel/i855pm/reset_test.c" +#include "lib/generic_sdram.c" + +static void main(unsigned long bist) +{ + static const struct mem_controller memctrl[] = { + { + .d0 = PCI_DEV(0, 0, 1), + .channel0 = { (0xa<<3)|0, 0 }, + }, + }; + + if (bist == 0) { + early_mtrr_init(); +#if 0 + enable_lapic(); + init_timer(); +#endif + } + + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + uart_init(); + console_init(); + + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + +#if 0 + print_pci_devices(); +#endif + + if(!bios_reset_detected()) { + enable_smbus(); +#if 0 + dump_spd_registers(&memctrl[0]); + // dump_smbus_registers(); +#endif + + + memreset_setup(); + + sdram_initialize(ARRAY_SIZE(memctrl), memctrl); + + } +#if 0 + else { + /* clear memory 1meg */ + __asm__ volatile( + "1: \n\t" + "movl %0, %%fs:(%1)\n\t" + "addl $4,%1\n\t" + "subl $4,%2\n\t" + "jnz 1b\n\t" + : + : "a" (0), "D" (0), "c" (1024*1024) + ); + + } +#endif + +#if 0 + dump_pci_devices(); +#endif +#if 0 + dump_pci_device(PCI_DEV(0, 0, 0)); +#endif + +/* +#if 0 + ram_check(0x00000000, msr.lo+(msr.hi<<32)); +#else +#if 0 + // Check 16MB of memory @ 0 + ram_check(0x00000000, 0x01000000); +#else + // Check 16MB of memory @ 2GB + ram_check(0x80000000, 0x81000000); +#endif +#endif +*/ +} diff --git a/src/mainboard/digitallogic/msm586seg/auto.c b/src/mainboard/digitallogic/msm586seg/auto.c deleted file mode 100644 index 8f1756b999..0000000000 --- a/src/mainboard/digitallogic/msm586seg/auto.c +++ /dev/null @@ -1,281 +0,0 @@ -#define ASSEMBLY 1 -#define __PRE_RAM__ -#define ASM_CONSOLE_LOGLEVEL 8 -#include -#include -#include -#include -#include -#include -#include "pc80/mc146818rtc_early.c" -#include "pc80/serial.c" -#include "arch/i386/lib/console.c" -#include "lib/ramtest.c" -#include "cpu/x86/bist.h" -//#include "lib/delay.c" - -void setup_pars(void) -{ - volatile unsigned long *par; - /* as per the book: */ - /* PAR register setup */ - /* set up the PAR registers as they are on the MSM586SEG */ - par = (unsigned long *) 0xfffef088; - - /* NOTE: move this to mainboard.c ASAP */ - *par++ = 0x607c00a0; /*PAR0: PCI:Base 0xa0000; size 0x1f000:*/ - *par++ = 0x480400d8; /*PAR1: GP BUS MEM:CS2:Base 0xd8, size 0x4:*/ - *par++ = 0x340100ea; /*PAR2: GP BUS IO:CS5:Base 0xea, size 0x1:*/ - *par++ = 0x380701f0; /*PAR3: GP BUS IO:CS6:Base 0x1f0, size 0x7:*/ - *par++ = 0x3c0003f6; /*PAR4: GP BUS IO:CS7:Base 0x3f6, size 0x0:*/ - *par++ = 0x35ff0400; /*PAR5: GP BUS IO:CS5:Base 0x400, size 0xff:*/ - *par++ = 0x35ff0600; /*PAR6: GP BUS IO:CS5:Base 0x600, size 0xff:*/ - *par++ = 0x35ff0800; /*PAR7: GP BUS IO:CS5:Base 0x800, size 0xff:*/ - *par++ = 0x35ff0a00; /*PAR8: GP BUS IO:CS5:Base 0xa00, size 0xff:*/ - *par++ = 0x35ff0e00; /*PAR9: GP BUS IO:CS5:Base 0xe00, size 0xff:*/ - *par++ = 0x34fb0104; /*PAR10: GP BUS IO:CS5:Base 0x104, size 0xfb:*/ - *par++ = 0x35af0200; /*PAR11: GP BUS IO:CS5:Base 0x200, size 0xaf:*/ - *par++ = 0x341f03e0; /*PAR12: GP BUS IO:CS5:Base 0x3e0, size 0x1f:*/ - *par++ = 0xe41c00c0; /*PAR13: SDRAM:code:cache:nowrite:Base 0xc0000, size 0x7000:*/ - *par++ = 0x545c00c8; /*PAR14: GP BUS MEM:CS5:Base 0xc8, size 0x5c:*/ - *par++ = 0x8a020200; /*PAR15: BOOTCS:code:nocache:write:Base 0x2000000, size 0x80000:*/ -} - -#include "cpu/amd/sc520/raminit.c" - -typedef void (*lj)(void); - - - -struct mem_controller { - int i; -}; - -static void memreset_setup(void) -{ -} - -static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} - - - -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} - -static inline int spd_read_byte(unsigned device, unsigned address) -{ -// return smbus_read_byte(device, address); -} - -//#include "lib/generic_sdram.c" - -static inline void dumpmem(void){ - int i, j; - unsigned char *l; - unsigned char c; - - for(i = 0x4000; i < 0x5000; i += 16) { - print_err_hex32(i); print_err(":"); - for(j = 0; j < 16; j++) { - l = (unsigned char *)i + j; - c = *l; - print_err_hex8(c); - print_err(" "); - } - print_err("\r\n"); - } -} - - -static inline void irqinit(void){ - volatile unsigned char *cp; -#if 0 -/* these values taken from the msm board itself. - * and they cause the board to not even come out of calibrating_delay_loop - * if you can believe it. Our problem right now is no IDE or serial interrupts - * So we'll try to put interrupts in, one at a time. IDE first. - */ - cp = (volatile unsigned char *) 0xfffefd00; - *cp = 0x11; - cp = (volatile unsigned char *) 0xfffefd02; - *cp = 0x02; - cp = (volatile unsigned char *) 0xfffefd03; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd04; - *cp = 0xf7; - cp = (volatile unsigned char *) 0xfffefd08; - *cp = 0xf7; - cp = (volatile unsigned char *) 0xfffefd0a; - *cp = 0x8b; - cp = (volatile unsigned char *) 0xfffefd10; - *cp = 0x18; - cp = (volatile unsigned char *) 0xfffefd14; - *cp = 0x09; - cp = (volatile unsigned char *) 0xfffefd18; - *cp = 0x88; - cp = (volatile unsigned char *) 0xfffefd1a; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd1b; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd1c; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd20; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd21; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd22; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd28; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd29; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd30; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd31; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd32; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd33; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd40; - *cp = 0x10; - cp = (volatile unsigned char *) 0xfffefd41; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd42; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd43; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd44; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd45; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd46; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd50; - *cp = 0x37; - cp = (volatile unsigned char *) 0xfffefd51; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd52; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd53; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd54; - *cp = 0x37; - cp = (volatile unsigned char *) 0xfffefd55; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd56; - *cp = 0x37; - cp = (volatile unsigned char *) 0xfffefd57; - *cp = 0x00; - cp = (volatile unsigned char *) 0xfffefd58; - *cp = 0xff; - cp = (volatile unsigned char *) 0xfffefd59; - *cp = 0xff; - cp = (volatile unsigned char *) 0xfffefd5a; - *cp = 0xff; -#endif -#if 0 - /* this fails too */ - /* IDE only ... */ - cp = (volatile unsigned char *) 0xfffefd56; - *cp = 0xe; -#endif -} - - - -static void main(unsigned long bist) -{ - volatile int i; - for(i = 0; i < 100; i++) - ; - - - setupsc520(); - irqinit(); - uart_init(); - console_init(); - for(i = 0; i < 100; i++) - print_err("fill usart\r\n"); - // while(1) - print_err("HI THERE!\r\n"); - // sizemem(); - staticmem(); - print_err("c60 is "); print_err_hex16(*(unsigned short *)0xfffefc60); - print_err("\n"); - - // while(1) - print_err("STATIC MEM DONE\r\n"); - outb(0xee, 0x80); - print_err("loop forever ...\n"); - - -#if 0 - - /* clear memory 1meg */ - __asm__ volatile( - "1: \n\t" - "movl %0, %%fs:(%1)\n\t" - "addl $4,%1\n\t" - "subl $4,%2\n\t" - "jnz 1b\n\t" - : - : "a" (0), "D" (0), "c" (1024*1024) - ); - - -#endif - -#if 0 - dump_pci_devices(); -#endif -#if 0 - dump_pci_device(PCI_DEV(0, 0, 0)); -#endif - -#if 0 - print_err("RAM CHECK!\r\n"); - // Check 16MB of memory @ 0 - ram_check(0x00000000, 0x01000000); -#endif -#if 0 - print_err("RAM CHECK for 32 MB!\r\n"); - // Check 32MB of memory @ 0 - ram_check(0x00000000, 0x02000000); -#endif -#if 1 - { - volatile unsigned char *src = (unsigned char *) 0x2000000 + 0x60000; - volatile unsigned char *dst = (unsigned char *) 0x4000; - for(i = 0; i < 0x20000; i++) { - /* - print_err("Set dst "); print_err_hex32((unsigned long) dst); - print_err(" to "); print_err_hex32(*src); print_err("\r\n"); - */ - *dst = *src; - //print_err(" dst is now "); print_err_hex32(*dst); print_err("\r\n"); - dst++, src++; - outb((unsigned char)i, 0x80); - } - } - dumpmem(); - outb(0, 0x80); - print_err("loop forever\r\n"); - outb(0xdd, 0x80); - __asm__ volatile( - "movl %0, %%edi\n\t" - "jmp *%%edi\n\t" - : - : "a" (0x4000) - ); - - print_err("Oh dear, I'm afraid it didn't work...\r\n"); - - while(1); -#endif -} - diff --git a/src/mainboard/digitallogic/msm586seg/romstage.c b/src/mainboard/digitallogic/msm586seg/romstage.c new file mode 100644 index 0000000000..8f1756b999 --- /dev/null +++ b/src/mainboard/digitallogic/msm586seg/romstage.c @@ -0,0 +1,281 @@ +#define ASSEMBLY 1 +#define __PRE_RAM__ +#define ASM_CONSOLE_LOGLEVEL 8 +#include +#include +#include +#include +#include +#include +#include "pc80/mc146818rtc_early.c" +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "lib/ramtest.c" +#include "cpu/x86/bist.h" +//#include "lib/delay.c" + +void setup_pars(void) +{ + volatile unsigned long *par; + /* as per the book: */ + /* PAR register setup */ + /* set up the PAR registers as they are on the MSM586SEG */ + par = (unsigned long *) 0xfffef088; + + /* NOTE: move this to mainboard.c ASAP */ + *par++ = 0x607c00a0; /*PAR0: PCI:Base 0xa0000; size 0x1f000:*/ + *par++ = 0x480400d8; /*PAR1: GP BUS MEM:CS2:Base 0xd8, size 0x4:*/ + *par++ = 0x340100ea; /*PAR2: GP BUS IO:CS5:Base 0xea, size 0x1:*/ + *par++ = 0x380701f0; /*PAR3: GP BUS IO:CS6:Base 0x1f0, size 0x7:*/ + *par++ = 0x3c0003f6; /*PAR4: GP BUS IO:CS7:Base 0x3f6, size 0x0:*/ + *par++ = 0x35ff0400; /*PAR5: GP BUS IO:CS5:Base 0x400, size 0xff:*/ + *par++ = 0x35ff0600; /*PAR6: GP BUS IO:CS5:Base 0x600, size 0xff:*/ + *par++ = 0x35ff0800; /*PAR7: GP BUS IO:CS5:Base 0x800, size 0xff:*/ + *par++ = 0x35ff0a00; /*PAR8: GP BUS IO:CS5:Base 0xa00, size 0xff:*/ + *par++ = 0x35ff0e00; /*PAR9: GP BUS IO:CS5:Base 0xe00, size 0xff:*/ + *par++ = 0x34fb0104; /*PAR10: GP BUS IO:CS5:Base 0x104, size 0xfb:*/ + *par++ = 0x35af0200; /*PAR11: GP BUS IO:CS5:Base 0x200, size 0xaf:*/ + *par++ = 0x341f03e0; /*PAR12: GP BUS IO:CS5:Base 0x3e0, size 0x1f:*/ + *par++ = 0xe41c00c0; /*PAR13: SDRAM:code:cache:nowrite:Base 0xc0000, size 0x7000:*/ + *par++ = 0x545c00c8; /*PAR14: GP BUS MEM:CS5:Base 0xc8, size 0x5c:*/ + *par++ = 0x8a020200; /*PAR15: BOOTCS:code:nocache:write:Base 0x2000000, size 0x80000:*/ +} + +#include "cpu/amd/sc520/raminit.c" + +typedef void (*lj)(void); + + + +struct mem_controller { + int i; +}; + +static void memreset_setup(void) +{ +} + +static void memreset(int controllers, const struct mem_controller *ctrl) +{ +} + + + +static inline void activate_spd_rom(const struct mem_controller *ctrl) +{ + /* nothing to do */ +} + +static inline int spd_read_byte(unsigned device, unsigned address) +{ +// return smbus_read_byte(device, address); +} + +//#include "lib/generic_sdram.c" + +static inline void dumpmem(void){ + int i, j; + unsigned char *l; + unsigned char c; + + for(i = 0x4000; i < 0x5000; i += 16) { + print_err_hex32(i); print_err(":"); + for(j = 0; j < 16; j++) { + l = (unsigned char *)i + j; + c = *l; + print_err_hex8(c); + print_err(" "); + } + print_err("\r\n"); + } +} + + +static inline void irqinit(void){ + volatile unsigned char *cp; +#if 0 +/* these values taken from the msm board itself. + * and they cause the board to not even come out of calibrating_delay_loop + * if you can believe it. Our problem right now is no IDE or serial interrupts + * So we'll try to put interrupts in, one at a time. IDE first. + */ + cp = (volatile unsigned char *) 0xfffefd00; + *cp = 0x11; + cp = (volatile unsigned char *) 0xfffefd02; + *cp = 0x02; + cp = (volatile unsigned char *) 0xfffefd03; + *cp = 0x00; + cp = (volatile unsigned char *) 0xfffefd04; + *cp = 0xf7; + cp = (volatile unsigned char *) 0xfffefd08; + *cp = 0xf7; + cp = (volatile unsigned char *) 0xfffefd0a; + *cp = 0x8b; + cp = (volatile unsigned char *) 0xfffefd10; + *cp = 0x18; + cp = (volatile unsigned char *) 0xfffefd14; + *cp = 0x09; + cp = (volatile unsigned char *) 0xfffefd18; + *cp = 0x88; + cp = (volatile unsigned char *) 0xfffefd1a; + *cp = 0x00; + cp = (volatile unsigned char *) 0xfffefd1b; + *cp = 0x00; + cp = (volatile unsigned char *) 0xfffefd1c; + *cp = 0x00; + cp = (volatile unsigned char *) 0xfffefd20; + *cp = 0x00; + cp = (volatile unsigned char *) 0xfffefd21; + *cp = 0x00; + cp = (volatile unsigned char *) 0xfffefd22; + *cp = 0x00; + cp = (volatile unsigned char *) 0xfffefd28; + *cp = 0x00; + cp = (volatile unsigned char *) 0xfffefd29; + *cp = 0x00; + cp = (volatile unsigned char *) 0xfffefd30; + *cp = 0x00; + cp = (volatile unsigned char *) 0xfffefd31; + *cp = 0x00; + cp = (volatile unsigned char *) 0xfffefd32; + *cp = 0x00; + cp = (volatile unsigned char *) 0xfffefd33; + *cp = 0x00; + cp = (volatile unsigned char *) 0xfffefd40; + *cp = 0x10; + cp = (volatile unsigned char *) 0xfffefd41; + *cp = 0x00; + cp = (volatile unsigned char *) 0xfffefd42; + *cp = 0x00; + cp = (volatile unsigned char *) 0xfffefd43; + *cp = 0x00; + cp = (volatile unsigned char *) 0xfffefd44; + *cp = 0x00; + cp = (volatile unsigned char *) 0xfffefd45; + *cp = 0x00; + cp = (volatile unsigned char *) 0xfffefd46; + *cp = 0x00; + cp = (volatile unsigned char *) 0xfffefd50; + *cp = 0x37; + cp = (volatile unsigned char *) 0xfffefd51; + *cp = 0x00; + cp = (volatile unsigned char *) 0xfffefd52; + *cp = 0x00; + cp = (volatile unsigned char *) 0xfffefd53; + *cp = 0x00; + cp = (volatile unsigned char *) 0xfffefd54; + *cp = 0x37; + cp = (volatile unsigned char *) 0xfffefd55; + *cp = 0x00; + cp = (volatile unsigned char *) 0xfffefd56; + *cp = 0x37; + cp = (volatile unsigned char *) 0xfffefd57; + *cp = 0x00; + cp = (volatile unsigned char *) 0xfffefd58; + *cp = 0xff; + cp = (volatile unsigned char *) 0xfffefd59; + *cp = 0xff; + cp = (volatile unsigned char *) 0xfffefd5a; + *cp = 0xff; +#endif +#if 0 + /* this fails too */ + /* IDE only ... */ + cp = (volatile unsigned char *) 0xfffefd56; + *cp = 0xe; +#endif +} + + + +static void main(unsigned long bist) +{ + volatile int i; + for(i = 0; i < 100; i++) + ; + + + setupsc520(); + irqinit(); + uart_init(); + console_init(); + for(i = 0; i < 100; i++) + print_err("fill usart\r\n"); + // while(1) + print_err("HI THERE!\r\n"); + // sizemem(); + staticmem(); + print_err("c60 is "); print_err_hex16(*(unsigned short *)0xfffefc60); + print_err("\n"); + + // while(1) + print_err("STATIC MEM DONE\r\n"); + outb(0xee, 0x80); + print_err("loop forever ...\n"); + + +#if 0 + + /* clear memory 1meg */ + __asm__ volatile( + "1: \n\t" + "movl %0, %%fs:(%1)\n\t" + "addl $4,%1\n\t" + "subl $4,%2\n\t" + "jnz 1b\n\t" + : + : "a" (0), "D" (0), "c" (1024*1024) + ); + + +#endif + +#if 0 + dump_pci_devices(); +#endif +#if 0 + dump_pci_device(PCI_DEV(0, 0, 0)); +#endif + +#if 0 + print_err("RAM CHECK!\r\n"); + // Check 16MB of memory @ 0 + ram_check(0x00000000, 0x01000000); +#endif +#if 0 + print_err("RAM CHECK for 32 MB!\r\n"); + // Check 32MB of memory @ 0 + ram_check(0x00000000, 0x02000000); +#endif +#if 1 + { + volatile unsigned char *src = (unsigned char *) 0x2000000 + 0x60000; + volatile unsigned char *dst = (unsigned char *) 0x4000; + for(i = 0; i < 0x20000; i++) { + /* + print_err("Set dst "); print_err_hex32((unsigned long) dst); + print_err(" to "); print_err_hex32(*src); print_err("\r\n"); + */ + *dst = *src; + //print_err(" dst is now "); print_err_hex32(*dst); print_err("\r\n"); + dst++, src++; + outb((unsigned char)i, 0x80); + } + } + dumpmem(); + outb(0, 0x80); + print_err("loop forever\r\n"); + outb(0xdd, 0x80); + __asm__ volatile( + "movl %0, %%edi\n\t" + "jmp *%%edi\n\t" + : + : "a" (0x4000) + ); + + print_err("Oh dear, I'm afraid it didn't work...\r\n"); + + while(1); +#endif +} + diff --git a/src/mainboard/digitallogic/msm800sev/Makefile.inc b/src/mainboard/digitallogic/msm800sev/Makefile.inc index f101f22d4e..0e4b263223 100644 --- a/src/mainboard/digitallogic/msm800sev/Makefile.inc +++ b/src/mainboard/digitallogic/msm800sev/Makefile.inc @@ -12,7 +12,7 @@ crt0s += $(src)/cpu/x86/32bit/entry32.inc crt0s += $(src)/cpu/x86/16bit/reset16.inc crt0s += $(src)/arch/i386/lib/id.inc crt0s += $(src)/cpu/amd/model_lx/cache_as_ram.inc -crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/auto.inc +crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc ldscripts := $(src)/arch/i386/init/ldscript_fallback_cbfs.lb ldscripts += $(src)/cpu/x86/16bit/entry16.lds @@ -22,8 +22,8 @@ ldscripts += $(src)/arch/i386/lib/failover.lds ifdef POST_EVALUATION -$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/build.h - $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@ +$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/build.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@ perl -e 's/\.rodata/.rom.data/g' -pi $@ perl -e 's/\.text/.section .rom.text/g' -pi $@ diff --git a/src/mainboard/digitallogic/msm800sev/auto.c b/src/mainboard/digitallogic/msm800sev/auto.c deleted file mode 100644 index 29a5661d85..0000000000 --- a/src/mainboard/digitallogic/msm800sev/auto.c +++ /dev/null @@ -1,138 +0,0 @@ -#define ASSEMBLY 1 -#define __PRE_RAM__ - -#include -#include -#include -#include -#include -#include -#include "pc80/serial.c" -#include "arch/i386/lib/console.c" -#include "lib/ramtest.c" -//#include "superio/winbond/w83627hf/w83627hf_early_serial.c" -#include "cpu/x86/bist.h" -#include "cpu/x86/msr.h" -#include - -//#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) - -#include "southbridge/amd/cs5536/cs5536_early_smbus.c" -#include "southbridge/amd/cs5536/cs5536_early_setup.c" - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -#include "northbridge/amd/lx/raminit.h" - -static inline unsigned int fls(unsigned int x) -{ - int r; - - __asm__("bsfl %1,%0\n\t" - "jnz 1f\n\t" - "movl $32,%0\n" - "1:" : "=r" (r) : "g" (x)); - return r; -} - - - -static void sdram_set_spd_registers(const struct mem_controller *ctrl) -{ - /* Total size of DIMM = 2^row address (byte 3) * 2^col address (byte 4) * - * component Banks (byte 17) * module banks, side (byte 5) * - * width in bits (byte 6,7) - * = Density per side (byte 31) * number of sides (byte 5) */ - /* 1. Initialize GLMC registers base on SPD values, do one DIMM for now */ - msr_t msr; - unsigned char module_banks, val; - - - msr.hi = 0x10075012; - msr.lo = 0x00000040; - - wrmsr(MC_CF07_DATA, msr); //GX3 - - /* timing and mode ... */ - - //msr = rdmsr(0x20000019); - - /* per standard bios settings */ -/* - msr.hi = 0x18000108; - msr.lo = - (6<<28) | // cas_lat - (10<<24)| // ref2act - (7<<20)| // act2pre - (3<<16)| // pre2act - (3<<12)| // act2cmd - (2<<8)| // act2act - (2<<6)| // dplwr - (2<<4)| // dplrd - (3); // dal - * the msr value reported by quanta is very, very different. - * we will go with that value for now. - * - //msr.lo = 0x286332a3; -*/ - //wrmsr(0x20000019, msr); //GX3 - -} - -#include "northbridge/amd/lx/raminit.c" -#include "lib/generic_sdram.c" - -/* CPU and GLIU mult/div */ -#define PLLMSRhi 0x0000039C -/* Hold Count - how long we will sit in reset */ -#define PLLMSRlo 0x00DE0000 - -#include "northbridge/amd/lx/pll_reset.c" -#include "cpu/amd/model_lx/cpureginit.c" -#include "cpu/amd/model_lx/syspreinit.c" -static void msr_init(void) -{ - - __builtin_wrmsr(0x10000020, 0xfff80, 0x20000000); - __builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000); - - __builtin_wrmsr(0x40000020, 0xfff80, 0x20000000); - __builtin_wrmsr(0x40000021, 0x80fffe0, 0x20000000); -} - - -static void main(unsigned long bist) -{ - static const struct mem_controller memctrl [] = { - {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}} - }; - - SystemPreInit(); //GX3 OK - - msr_init(); //GX3 OK - - cs5536_early_setup(); //GX3 OK - - /* NOTE: must do this AFTER the early_setup! - * it is counting on some early MSR setup - * for cs5536 - */ - cs5536_setup_onchipuart(); //GX3 OK - - uart_init(); //GX3 OK - console_init(); //GX3 OK - - pll_reset(); //GX3 OK - - cpuRegInit(); //GX3 OK - - print_err("done cpuRegInit\n"); - - sdram_initialize(1, memctrl); //GX3 OK almost - - /* Check all of memory */ - //ram_check(0x00000000, 640*1024); -} diff --git a/src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c b/src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c deleted file mode 100644 index 70fa935a8d..0000000000 --- a/src/mainboard/digitallogic/msm800sev/cache_as_ram_auto.c +++ /dev/null @@ -1,120 +0,0 @@ -#define ASSEMBLY 1 -#define __PRE_RAM__ - -#include -#include -#include -#include -#include -#include -#include "pc80/serial.c" -#include "arch/i386/lib/console.c" -#include "lib/ramtest.c" -#include "cpu/x86/bist.h" -#include "cpu/x86/msr.h" -#include -#include -#include "southbridge/amd/cs5536/cs5536.h" - -#define POST_CODE(x) outb(x, 0x80) -#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) - -#include "southbridge/amd/cs5536/cs5536_early_smbus.c" -#include "southbridge/amd/cs5536/cs5536_early_setup.c" -#include "superio/winbond/w83627hf/w83627hf_early_serial.c" - -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - -#define ManualConf 0 /* Do automatic strapped PLL config */ -#define PLLMSRhi 0x00001490 /* manual settings for the PLL */ -#define PLLMSRlo 0x02000030 -#define DIMM0 0xA0 -#define DIMM1 0xA2 -#include "northbridge/amd/lx/raminit.h" -#include "northbridge/amd/lx/pll_reset.c" -#include "northbridge/amd/lx/raminit.c" -#include "lib/generic_sdram.c" -#include "cpu/amd/model_lx/cpureginit.c" -#include "cpu/amd/model_lx/syspreinit.c" - -static void msr_init(void) -{ - msr_t msr; - /* Setup access to the MC for under 1MB. Note MC not setup yet. */ - msr.hi = 0x24fffc02; - msr.lo = 0x10010000; - wrmsr(CPU_RCONF_DEFAULT, msr); - - msr.hi = 0x20000000; - msr.lo = 0xfff00; - wrmsr(MSR_GLIU0 + 0x20, msr); - - msr.hi = 0x20000000; - msr.lo = 0xfff00; - wrmsr(MSR_GLIU1 + 0x20, msr); - -} - -static void mb_gpio_init(void) -{ - /* Early mainboard specific GPIO setup */ -} - -void cache_as_ram_main(void) -{ - extern void RestartCAR(); - POST_CODE(0x01); - - static const struct mem_controller memctrl [] = { - {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}} - }; - - SystemPreInit(); - msr_init(); - - cs5536_early_setup(); - - /* NOTE: must do this AFTER the early_setup! - * it is counting on some early MSR setup - * for cs5536 - */ - cs5536_disable_internal_uart(); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - mb_gpio_init(); - uart_init(); - console_init(); - - pll_reset(ManualConf); - - cpuRegInit(); - - sdram_initialize(1, memctrl); - - /* Check all of memory */ - ram_check(0x00000000, 640*1024); - - /* Switch from Cache as RAM to real RAM */ - /* There are two ways we could think about this. - 1. If we are using the auto.inc ROMCC way, the stack is going to be re-setup in the code following this code. - Just wbinvd the stack to clear the cache tags. We don't care where the stack used to be. - 2. This file is built as a normal .c -> .o and linked in etc. The stack might be used to return etc. - That means we care about what is in the stack. If we are smart we set the CAR stack to the same location - as the rest of coreboot. If that is the case we can just do a wbinvd. The stack will be written into real - RAM that is now setup and we continue like nothing happened. If the stack is located somewhere other than - where LB would like it, you need to write some code to do a copy from cache to RAM - - We use method 1 on Norwich. - */ - POST_CODE(0x02); - print_err("POST 02\n"); - __asm__("wbinvd\n"); - print_err("Past wbinvd\n"); - /* we are finding the return does not work on this board. Explicitly call the label that is - * after the call to us. This is gross, but sometimes at this level it is the only way out - */ - void done_cache_as_ram_main(void); - done_cache_as_ram_main(); -} diff --git a/src/mainboard/digitallogic/msm800sev/romstage.c b/src/mainboard/digitallogic/msm800sev/romstage.c new file mode 100644 index 0000000000..03f9fae57b --- /dev/null +++ b/src/mainboard/digitallogic/msm800sev/romstage.c @@ -0,0 +1,120 @@ +#define ASSEMBLY 1 +#define __PRE_RAM__ + +#include +#include +#include +#include +#include +#include +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "lib/ramtest.c" +#include "cpu/x86/bist.h" +#include "cpu/x86/msr.h" +#include +#include +#include "southbridge/amd/cs5536/cs5536.h" + +#define POST_CODE(x) outb(x, 0x80) +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) + +#include "southbridge/amd/cs5536/cs5536_early_smbus.c" +#include "southbridge/amd/cs5536/cs5536_early_setup.c" +#include "superio/winbond/w83627hf/w83627hf_early_serial.c" + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +#define ManualConf 0 /* Do automatic strapped PLL config */ +#define PLLMSRhi 0x00001490 /* manual settings for the PLL */ +#define PLLMSRlo 0x02000030 +#define DIMM0 0xA0 +#define DIMM1 0xA2 +#include "northbridge/amd/lx/raminit.h" +#include "northbridge/amd/lx/pll_reset.c" +#include "northbridge/amd/lx/raminit.c" +#include "lib/generic_sdram.c" +#include "cpu/amd/model_lx/cpureginit.c" +#include "cpu/amd/model_lx/syspreinit.c" + +static void msr_init(void) +{ + msr_t msr; + /* Setup access to the MC for under 1MB. Note MC not setup yet. */ + msr.hi = 0x24fffc02; + msr.lo = 0x10010000; + wrmsr(CPU_RCONF_DEFAULT, msr); + + msr.hi = 0x20000000; + msr.lo = 0xfff00; + wrmsr(MSR_GLIU0 + 0x20, msr); + + msr.hi = 0x20000000; + msr.lo = 0xfff00; + wrmsr(MSR_GLIU1 + 0x20, msr); + +} + +static void mb_gpio_init(void) +{ + /* Early mainboard specific GPIO setup */ +} + +void cache_as_ram_main(void) +{ + extern void RestartCAR(); + POST_CODE(0x01); + + static const struct mem_controller memctrl [] = { + {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}} + }; + + SystemPreInit(); + msr_init(); + + cs5536_early_setup(); + + /* NOTE: must do this AFTER the early_setup! + * it is counting on some early MSR setup + * for cs5536 + */ + cs5536_disable_internal_uart(); + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + mb_gpio_init(); + uart_init(); + console_init(); + + pll_reset(ManualConf); + + cpuRegInit(); + + sdram_initialize(1, memctrl); + + /* Check all of memory */ + ram_check(0x00000000, 640*1024); + + /* Switch from Cache as RAM to real RAM */ + /* There are two ways we could think about this. + 1. If we are using the romstage.inc ROMCC way, the stack is going to be re-setup in the code following this code. + Just wbinvd the stack to clear the cache tags. We don't care where the stack used to be. + 2. This file is built as a normal .c -> .o and linked in etc. The stack might be used to return etc. + That means we care about what is in the stack. If we are smart we set the CAR stack to the same location + as the rest of coreboot. If that is the case we can just do a wbinvd. The stack will be written into real + RAM that is now setup and we continue like nothing happened. If the stack is located somewhere other than + where LB would like it, you need to write some code to do a copy from cache to RAM + + We use method 1 on Norwich. + */ + POST_CODE(0x02); + print_err("POST 02\n"); + __asm__("wbinvd\n"); + print_err("Past wbinvd\n"); + /* we are finding the return does not work on this board. Explicitly call the label that is + * after the call to us. This is gross, but sometimes at this level it is the only way out + */ + void done_cache_as_ram_main(void); + done_cache_as_ram_main(); +} -- cgit v1.2.3