From d87321c8a5cefdf1fa5d99dbad2c0f3b1efc71b5 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Sat, 10 Aug 2024 22:06:41 +0200 Subject: mb/cwwk/adl/devicetree: enable all USB ports The cw-al-4l-v1.0 mainboard has two USB2 ports on a 2x5 pin header on the mainboard and likely also routes one USB2 port to the m.2 E key slot which is typically used for Bluetooth support when an E key m.2 WIFI + Bluetooth card is installed. This is untested, since I only have the cw-al-4l-v2.0 mainboard, but from looking at the documentation of the version 1 and looking at how things are done on the version 2 this should be correct. Signed-off-by: Felix Held Change-Id: I7059a3f2d9cde0086382a4484c09d5ef33dc906d Reviewed-on: https://review.coreboot.org/c/coreboot/+/83910 Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier --- src/mainboard/cwwk/adl/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/mainboard/cwwk/adl') diff --git a/src/mainboard/cwwk/adl/devicetree.cb b/src/mainboard/cwwk/adl/devicetree.cb index c4c5e8c132..86a31e759f 100644 --- a/src/mainboard/cwwk/adl/devicetree.cb +++ b/src/mainboard/cwwk/adl/devicetree.cb @@ -6,7 +6,10 @@ chip soc/intel/alderlake register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)" + register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)" + register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)" register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # microSD card reader + register "usb2_ports[7]" = "USB2_PORT_SHORT(OC_SKIP)" register "pch_pcie_rp[PCH_RP(1)]" = "{ .clk_src = 0, -- cgit v1.2.3