From 3fa42ac553e0e7583a0e8db2e8c34fbd09a07225 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Mon, 20 Jun 2022 21:22:27 +0200 Subject: mb/clevo/l140mu: work around PECI staying high when idle, blocking s0ix MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit According to Intel doc# 575683 the PECI bus should be low when idle and is pulled up by clients with strong drive. However, for unknown reasons the bus stays high on this board, blocking s0ix entry. The PECI reference schematic in the ASPEED AST2400 BMC datasheet (actually not related to this board) says that a pull-down is *required* for the idle state. This might be just a requirement of this BMC, since this is nowhere documented in Intel datasheets, schematics or elsewhere. However, configuring a weak pull-down (20 k) on the PECI pad indeed solves this problem for now. Change-Id: I85193000af67cd2c0465bdbb58cdd51b68fd5b4f Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/68794 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/clevo/tgl-u/variants/l140mu/gpio.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/mainboard/clevo') diff --git a/src/mainboard/clevo/tgl-u/variants/l140mu/gpio.c b/src/mainboard/clevo/tgl-u/variants/l140mu/gpio.c index 6919baf418..831b5fe9b1 100644 --- a/src/mainboard/clevo/tgl-u/variants/l140mu/gpio.c +++ b/src/mainboard/clevo/tgl-u/variants/l140mu/gpio.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -232,4 +233,7 @@ static const struct pad_config gpio_table[] = { void variant_configure_gpios(void) { gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + + /* PECI idle workaround */ + pcr_rmw32(0x6b, 0x744, ~PAD_CFG1_PULL_MASK, PAD_CFG1_PULL_DN_20K); } -- cgit v1.2.3