From 2bc4b934c35ca14ab1243c19dc6fa27688feefdb Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Fri, 12 Jan 2024 16:22:19 +0100 Subject: soc/intel/tigerlake: Drop redundant PcieRpEnable The PcieRpEnable option is redundant to our on/off setting in the devicetrees. Let's use the common coreboot infrastructure instead. Thanks to Nicholas for doing all the mainboard legwork! Change-Id: Iacfef5f032278919f1fcf49e31fa42bcbf1eaf20 Signed-off-by: Nico Huber Signed-off-by: Nicholas Sudsgaard Reviewed-on: https://review.coreboot.org/c/coreboot/+/79920 Reviewed-by: Sean Rhodes Reviewed-by: Matt DeVillier Tested-by: build bot (Jenkins) --- src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb | 3 --- 1 file changed, 3 deletions(-) (limited to 'src/mainboard/clevo/tgl-u/variants/l140mu') diff --git a/src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb b/src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb index 73f32e3a5d..0131e21948 100644 --- a/src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb +++ b/src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb @@ -154,7 +154,6 @@ chip soc/intel/tigerlake end end device ref pcie_rp3 on - register "PcieRpEnable[2]" = "true" register "PcieRpLtrEnable[2]" = "true" register "PcieClkSrcUsage[1]" = "2" register "PcieClkSrcClkReq[1]" = "1" @@ -167,14 +166,12 @@ chip soc/intel/tigerlake device ref pcie_rp6 on # Card reader device pci 00.0 on end - register "PcieRpEnable[5]" = "true" register "PcieRpLtrEnable[5]" = "true" register "PcieClkSrcUsage[2]" = "5" register "PcieClkSrcClkReq[2]" = "2" end device ref pcie_rp9 on # SSD2 - PCIe mode - register "PcieRpEnable[8]" = "true" register "PcieRpLtrEnable[8]" = "true" register "PcieClkSrcUsage[0]" = "8" register "PcieClkSrcClkReq[0]" = "0" -- cgit v1.2.3