From e1269a7f21ed1cb408f80a9e4cf9616b4cecc135 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 30 Aug 2021 11:07:05 +0200 Subject: skylake DDR4 boards: Set `CaVrefConfig` to 2 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The `CaVrefConfig` FSP-M UPD describes how the on-die Vref generators are connected to the DRAM. With the exception of an early Skylake RVP board (which doesn't have coreboot support), mainboards using DDR3 or LPDDR3 memory should set `CaVrefConfig` to 0, whereas mainboards with DDR4 should set `CaVrefConfig` to 2. MRC uses this information during memory training, so it is important to use the correct value to avoid any issues, such as increased power usage, system instability or even boot failures. However, several Skylake DDR4 mainboards don't set `CaVrefConfig` to 2. Although they can boot successfully, it's not optimal. For boards that set `DIMM_SPD_SIZE` to 512 (DDR4 SPD size), set `CaVrefConfig` to 2. Change-Id: Idab77daff311584b3e3061e9bf107c2fc1b7bdf1 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/57262 Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer Reviewed-by: Michael Niewöhner --- src/mainboard/clevo/kbl-u/variants/n13xwu/romstage.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mainboard/clevo/kbl-u') diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/romstage.c b/src/mainboard/clevo/kbl-u/variants/n13xwu/romstage.c index 4e9d57c21a..116d418f63 100644 --- a/src/mainboard/clevo/kbl-u/variants/n13xwu/romstage.c +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/romstage.c @@ -32,6 +32,7 @@ void variant_configure_fspm(FSPM_UPD *mupd) mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); mem_cfg->DqPinsInterleaved = TRUE; + mem_cfg->CaVrefConfig = 2; mem_cfg->MemorySpdDataLen = blk.len; mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0]; mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1]; -- cgit v1.2.3