From 8e60571f6e751547a10a9db42817be404278bd01 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Sun, 27 Sep 2020 17:55:22 +0200 Subject: mb/clevo/cml-u: drop PcieRpSlotImplemented for card reader MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit PcieRpSlotImplemented should only be set to 1 for PCIe ports implementing a PCIe slot. Drop it for the on-board card reader. Change-Id: I22628b4d4a7e317a01e46a61b5cd7bb9ebf548a0 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/45776 Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer Reviewed-by: Angel Pons --- src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb | 1 - 1 file changed, 1 deletion(-) (limited to 'src/mainboard/clevo/cml-u/variants/l140cu') diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index 55c5c6ebf8..e079dffff9 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -138,7 +138,6 @@ chip soc/intel/cannonlake register "PcieRpLtrEnable[5]" = "1" register "PcieClkSrcUsage[3]" = "5" register "PcieClkSrcClkReq[3]" = "3" - register "PcieRpSlotImplemented[5]" = "1" end device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 on # PCI Express Port 8 -- cgit v1.2.3