From cb8eab482ff09ec256456312ef2d6e7710123551 Mon Sep 17 00:00:00 2001 From: Richard Smith Date: Mon, 24 Jul 2006 04:25:47 +0000 Subject: add framework for i440bx chipset add support for NSC pc87351 SuperIO add Bitworks/IMS manboard config This is a very basic framework for the i440bx chipset and the Bitworks IMS board that uses it. Most things are structure only. Known issues: - SMbus reads to the RAM SPD come back all zero. - dump_spd_registers() is commented out since it breaks with the default setting of generic_dump_spd.c where it wants 2 memory controllers. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2347 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/bitworks/ims/reset.c | 43 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 src/mainboard/bitworks/ims/reset.c (limited to 'src/mainboard/bitworks/ims/reset.c') diff --git a/src/mainboard/bitworks/ims/reset.c b/src/mainboard/bitworks/ims/reset.c new file mode 100644 index 0000000000..5796e17dc8 --- /dev/null +++ b/src/mainboard/bitworks/ims/reset.c @@ -0,0 +1,43 @@ +#if 0 +//#include "arch/romcc_io.h" +#include + +typedef unsigned device_t; + +#define PCI_DEV(BUS, DEV, FN) ( \ + (((BUS) & 0xFF) << 16) | \ + (((DEV) & 0x1f) << 11) | \ + (((FN) & 0x7) << 8)) + +static void pci_write_config8(device_t dev, unsigned where, unsigned char value) +{ + unsigned addr; + addr = dev | where; + outl(0x80000000 | (addr & ~3), 0xCF8); + outb(value, 0xCFC + (addr & 3)); +} + +static void pci_write_config32(device_t dev, unsigned where, unsigned value) +{ + unsigned addr; + addr = dev | where; + outl(0x80000000 | (addr & ~3), 0xCF8); + outl(value, 0xCFC); +} + +static unsigned pci_read_config32(device_t dev, unsigned where) +{ + unsigned addr; + addr = dev | where; + outl(0x80000000 | (addr & ~3), 0xCF8); + return inl(0xCFC); +} + +#include "../../../northbridge/amd/amdk8/reset_test.c" + +void hard_reset(void) +{ + set_bios_reset(); + pci_write_config8(PCI_DEV(1, 0x04, 0), 0x47, 1); +} +#endif -- cgit v1.2.3