From d777c780660bc8e5b4e531b5335e12bb56d8c700 Mon Sep 17 00:00:00 2001 From: Sergej Ivanov Date: Fri, 3 Apr 2015 18:10:27 +0300 Subject: mainboard/biostar: Add support for Biostar AM1ML ver7.x MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Adds AM1ML board. This board has AM1 Socket and supports all new AM1 APUs from AMD. Based on asrock/imb-a180 board. Successfully tested with SeaBIOS and Linux 3.8.x and Windows XP. Successfully tested audio, video, network, PS/2 keyboard and mouse, PCIe x16, COM port, SATA and USB. LPT port is not tested yet and it’s unknown if it’s work. Change-Id: I9ebb9acc590d38e47579adc263f45ae3f607684e Signed-off-by: Sergej Ivanov Reviewed-on: http://review.coreboot.org/9293 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Dave Frodin --- src/mainboard/biostar/am1ml/dsdt.asl | 99 ++++++++++++++++++++++++++++++++++++ 1 file changed, 99 insertions(+) create mode 100644 src/mainboard/biostar/am1ml/dsdt.asl (limited to 'src/mainboard/biostar/am1ml/dsdt.asl') diff --git a/src/mainboard/biostar/am1ml/dsdt.asl b/src/mainboard/biostar/am1ml/dsdt.asl new file mode 100644 index 0000000000..40b79b21c7 --- /dev/null +++ b/src/mainboard/biostar/am1ml/dsdt.asl @@ -0,0 +1,99 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * Copyright (C) 2015 Sergej Ivanov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* DefinitionBlock Statement */ +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "AMD ", /* OEMID */ + "COREBOOT", /* TABLE ID */ + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include */ /* Include global debug methods if needed */ + + /* Globals for the platform */ + #include "acpi/mainboard.asl" + + /* Describe the USB Overcurrent pins */ + #include "acpi/usb_oc.asl" + + /* PCI IRQ mapping for the Southbridge */ + #include + + /* Describe the processor tree (\_PR) */ + #include + + /* Contains the supported sleep states for this chipset */ + #include + + /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ + #include "acpi/sleep.asl" + + /* stuff for sio */ + #include "acpi/flag0.asl" + + /* System Bus */ + Scope(\_SB) { /* Start \_SB scope */ + /* global utility methods expected within the \_SB scope */ + #include + + /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ + #include "acpi/routing.asl" + + Device(PWRB) { + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) + Name(_STA, 0x0B) + } + + Device(PCI0) { + /* Describe the AMD Northbridge */ + #include + + /* Describe the AMD Fusion Controller Hub Southbridge */ + #include + + /* sio fixup */ + #include "acpi/sio.asl" + } + + /* Describe PCI INT[A-H] for the Southbridge */ + #include + + } /* End \_SB scope */ + + /* Describe SMBUS for the Southbridge */ + #include + + /* Define the General Purpose Events for the platform */ + #include "acpi/gpe.asl" + + /* Define the Thermal zones and methods for the platform */ + #include "acpi/thermal.asl" + + /* Define the System Indicators for the platform */ + #include "acpi/si.asl" + +} +/* End of ASL file */ -- cgit v1.2.3